W981216AH Datasheet, PDF (18/44 Pages) Winbond – 2M x 16 bit x 4 Banks SDRAM

Mode Register Set Cycle
CLK
CS
tCMS
tCMH
RAS
CAS
WE
A0-A10
BS
tCMS tCMH
tCMS tCMH
tCMS tCMH
tAS
tAH
Register
set data
A0
A1 Burst Length
A2
A3 Addressing Mode
A4
A5 CAS Latency
A6
A07 "0" (Test Mode)
A8 "0" Reserved
A09
WriteA0Mode
A10 "0"
AA101 "0"
BS0 "0"
ResAe0rved
BAS01 "0"
Revision 1.0
W981216AH
2M x 16 bit x 4 Banks SDRAM
tRSC
A0
A2 A10 A0
0 A00 0
0 A00 1
0 A10 0
0 A10 1
1 A00 0
1 A00 1
1 A10 0
1 A10 1
A03
A00
A10
A6 A50 A4
0 A00 0
0 A00 1
0 A10 0
0 A10 1
1 A00 0
A09
A00
A10
next
command
BurstAL0ength
SeqAue0ntial
InteArle0ave
1
A10
A20
A20
A40
A40
A80
A80
ResAe0rved
ResAe0rved
FullAP0age
AddressAin0g Mode
SeqAue0ntial
InteArle0ave
CAS LAa0tency
ResAe0rved
ResAe0rved
2
A30
4
Single Write Mode
Burst read aAn0d Burst write
Burst read aAnd0 single write
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Publication Release Date: March, 1999