W981216AH Datasheet, PDF (33/44 Pages) Winbond – 2M x 16 bit x 4 Banks SDRAM

W981216AH
Autoprecharge Timing ( Read Cycle )
(1) CAS Latency=2
( a ) burst length = 1
Command
DQ
( b ) burst length = 2
Command
DQ
( c ) burst length = 4
Command
DQ
( d ) burst length = 8
Command
DQ
(2) CAS Latency=3
( a ) burst length = 1
Command
DQ
( b ) burst length = 2
Command
DQ
( c ) burst length = 4
Command
DQ
( d ) burst length = 8
Command
DQ
0
Read
Read
Read
Read
Read
Read
Read
Read
1
AP
AP
2
3
4
Act
tRP
Q0
AP
Act
tRP
Q0 Q1
AP
Q0 Q1 Q2
Q0 Q1 Q2
Act
tRP
Q0
AP
tRP
Q0 Q1
AP
Q0 Q1
Q0 Q1
2M x 16 bit x 4 Banks SDRAM
5
6
7
8
9
10 11
Act
tRP
Q3
AP
Act
tRP
Q3 Q4 Q5 Q6 Q7
Act
Act
tRP
Q2 Q3
AP
Act
tRP
Q2 Q3 Q4 Q5 Q6 Q7
Note )
Read
represents the Read with Auto precharge command.
AP
represents the start of internal precharging.
Act
represents the Bank Activate command.
When the Auto precharge command is asserted, the period from Bank Activate command to
the start of internal precgarging must be at least t RAS(min).
Revision 1.0
- 33 -
Publication Release Date: March, 1999