W981216AH Datasheet, PDF (19/44 Pages) Winbond – 2M x 16 bit x 4 Banks SDRAM

W981216AH
Operating Timing Example
2M x 16 bit x 4 Banks SDRAM
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
CLK
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CS
RAS
CAS
tRC
tRAS
tRC
tRP
tRAS
tRC
tRAS
tRP
tRC
tRP
tRAS
WE
BS0
BS1
A10 RAa
tRCD
A0-A9, _RAa
CAw
A11
DQM
RBb
tRCD
RAc
tRCD
RBd
tRCD
RAe
RBb
CBx
RAc
CAy
RBd
CBz
RAe
CKE
DQ
Bank #0 Active
Bank #1
Bank #2
Idle
Bank #3
tRRD
tAC
aw0 aw1 aw2 aw3
tRRD
tAC
bx0 bx1 bx2 bx3
tRRD
tAC
tAC
cy0 cy1 ^cy2 cy3
tRRD
Read
Precharge
Active
Read
Active
Read
Precharge
Active
Precharge
Read
Active
Revision 1.0
- 19 -
Publication Release Date: March, 1999