W981216AH Datasheet, PDF (21/44 Pages) Winbond – 2M x 16 bit x 4 Banks SDRAM

W981216AH
2M x 16 bit x 4 Banks SDRAM
Interleaved Bank Read (Burst Length=8, CAS Latency=3)
CLK
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CS
RAS
CAS
tRC
tRAS
tRP
tRP
tRAS
tRC
tRAS
tRC
tRP
WE
BS0
BS1
A10
tRCD
RAa
RBb
tRCD
tRCD
RAc
A0-A9 _RAa
CAx
A11
DQM
RBb
CBy
RAc
CAz
CKE
DQ
tRRD
tAC
tAC
ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1
tRRD
tAC
by4 by5 by6 by7
CZ0
Bank #0 ^Active
Bank #1
Bank #2
Idle
Bank #3
Read
Precharge
Active
Precharge
Read
Active
Read
Precharge
Revision 1.0
- 21 -
Publication Release Date: March, 1999