W981216AH Datasheet, PDF (22/44 Pages) Winbond – 2M x 16 bit x 4 Banks SDRAM

W981216AH
2M x 16 bit x 4 Banks SDRAM
Interleaved Bank Read (Burst Length=8, CAS Latency=3, Autoprecharge)
(CLK = 100 MHz)
CLK
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
t RC
RAS
CAS
tRAS
tRC
tRP
tRAS
tRAS
tRP
WE
BS0
BS1
tRCD
A10 _RAa
RBb
tRCD
tRCD
RAc
A0-A9 _RAa
CAx
DQM
RBb
CBy
RAc
CAz
CKE
DQ
Bank #0 Active
Bank #1
Bank #2
Idle
Bank #3
tCAC
tCAC
ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1
tRRD
Read
Active
tRRD
AP*
Read
Active
* AP is the internal precharge start timing
tCAC
by4 by5 by6
CZ0
Read
AP*
Revision 1.0
- 22 -
Publication Release Date: March, 1999