W981216AH Datasheet, PDF (39/44 Pages) Winbond – 2M x 16 bit x 4 Banks SDRAM

W981216AH
Timing chart of Burst Stop cycle ( Burst stop Command )
2M x 16 bit x 4 Banks SDRAM
0
1
2
3
4
5
6
7
8
9
(3) Read cycle
( a ) CAS latency =2
Command Read
BST
DQ
( b )CAS latency = 3
Command
Read
Q0 Q1 Q2 Q3 Q4
BST
DQ
( c )CAS latency = 4
Command
Read
DQ
(2) Write cycle
Command Write
Q0 Q1 Q2 Q3 Q4
BST
Q0 Q1 Q2 Q3 Q4
BST
DQ D0 D1 D2 D3 _D4
10 11
Note )
BST
represents the Burst stop command
Revision 1.0
- 39 -
Publication Release Date: March, 1999