W981216AH Datasheet, PDF (35/44 Pages) Winbond – 2M x 16 bit x 4 Banks SDRAM

W981216AH
Autoprecharge timing ( Write Cycle )
(1) CAS Latency=2
( a ) burst length = 1
Command
DQ
( b ) burst length = 2
Command
DQ
( c ) burst length = 4
Command
DQ
( d ) burst length = 8
Command
0
1
2
Write AP
tWR
tRP
D0
Write
D0
AP
tWR
D1
Write
D0 D1 D2
Write
3
4
Act
Act
tRP
AP
tWR
D3
DQ
(2) CAS Latency=3
( a ) burst length = 1
Command
DQ
( b ) burst length = 2
Command
DQ
( c ) burst length = 4
Command
DQ
( d ) burst length = 8
Command
D0 D1 D2 D3 D4
Write AP
Act
tWR
tRP
D0
Write
AP
tWR
tRP
D0 D1
Write
AP
tWR
D0 D1 D2 D3
Write
DQ
D0
D1
D2
D3
D4
2M x 16 bit x 4 Banks SDRAM
5
6
7
8
9
10 11
Act
tRP
AP
tWR
D5 D6 D7
Act
tRP
Act
Act
tRP
AP
Act
tWR
tRP
D5 D6 D7
Note )
Write
represents the Write with Auto precharge command.
AP
represents the start of internal precharging.
Act
represents the Bank Activate command.
When the Auto precharge command is asserted, the period from Bank Activate
command to the start of internal precgarging must be at least tRAS(min)..
Revision 1.0
- 35 -
Publication Release Date: March, 1999