W981216AH Datasheet, PDF (42/44 Pages) Winbond – 2M x 16 bit x 4 Banks SDRAM

W981216AH
CKE/DQM Input timing ( Read cycle )
CLK cycle No.
1
2
3
External
CLK
Internal
CKE
DQM
DQ
Q1
Q2
Q3
2M x 16 bit x 4 Banks SDRAM
4
5
6
7
Q4
Q6
Open
Open
(1)
CLK cycle No. ¹
2
External
CLK
Internal
CKE
DQM
DQ
Q1
Q2
CLK cycle No.
1
2
External
CLK
Internal
CKE
DQM
DQ
Q1
Q2
3
4
5
6
7
Q3
Q4
(2)
3
4
5
Q6
Open
6
7
Q3
Q4
Q5
Q6
(3)
Revision 1.0
- 42 -
Publication Release Date: March, 1999