W981216AH Datasheet, PDF (30/44 Pages) Winbond – 2M x 16 bit x 4 Banks SDRAM

W981216AH
2M x 16 bit x 4 Banks SDRAM
SelfRefresh Cycle
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
tRP
RAS
CAS
WE
BS0,1
A10
A0-A9,
A11
DQM
CKE
tSB
tCKS
tCKS
tCKS
DQ
Self Refresh Cycle
All Banks
Precharge
Self Refresh
Entry
tRC
No Operation Cycle
Arbitrary Cycle
Revision 1.0
- 30 -
Publication Release Date: March, 1999