W981216AH Datasheet, PDF (37/44 Pages) Winbond – 2M x 16 bit x 4 Banks SDRAM

W981216AH
Timing Chart of Read to Write cycle
In the case of Burst Length=4
2M x 16 bit x 4 Banks SDRAM
0
1
2
3
4
5
6
7
8
9
10 11
(1) CAS Latency=2
( a ) Command
Read Write
DQM
DQ
D0 D1 D2 D3
( b ) Command
DQM
DQ
(2) CAS Latency=3
( a ) Command
DQM
DQ
( b ) Command
DQM
DQ
(3) CAS Latency=4
( a ) Command
DQM
DQ
( b ) Command
DQM
Read
Write
D0 D1 D2 D3
Read Write
D0 D1 D2 D3
Read
Write
D0 D1 D2 D3
Read Write
D0 D1 D2 D3
Read
Write
DQ
D0 D1 D2 D3
Note ) The Output data must be masked by DQM to avoid I/O conflict
Revision 1.0
- 37 -
Publication Release Date: March, 1999