W981216AH Datasheet, PDF (41/44 Pages) Winbond – 2M x 16 bit x 4 Banks SDRAM

W981216AH
CKE/DQM Input timing ( Write cycle )
CLK cycle No.
1
2
3
CLK
External
Internal
CKE
DQM
DQ
D1
D2
D3
2M x 16 bit x 4 Banks SDRAM
4
5
6
7
D5
D6
DQM MASK
(1)
CKE MASK
CLK cycle No.
1
2
CLK
External
Internal
CKE
DQM
DQ
D1
D2
CLK cycle No.
1
2
CLK
External
Internal
CKE
DQM
DQ
D1
D2
3
4
5
6
7
D3
D5
D6
DQM MASK
(2)
CKE MASK
3
4
5
6
7
D3
D4
CKE MASK
(3)
D5
D6
Revision 1.0
- 41 -
Publication Release Date: March, 1999