THS8200IPFP Datasheet, PDF (91/104 Pages) Texas Instruments – All-Format Oversampled Component Video/PC Graphics D/A System

THS8200-EP
www.ti.com
SLES253 – DECEMBER 2009
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP⁽¹⁾ MAX UNIT
t_fi
DAC output current
fall time
10 to 90% of full-scale, CLK = 80 MHz
3.5
4.2 ns
t_d
Analog output
delay
Measured from falling edge of CLKIN to 50%
of full-scale transition⁽⁹⁾
6.5
ns
t_sa
Analog output
settling time
Measured from 50% of full scale transition on output to output
settling, within 2%⁽¹⁰⁾
6.6
ns
SFDR
Spurious-free
dynamic range
1 MHz, −1 dB FS digital sine input
10 MHz, −1 dB FS digital sine input
–55
dB
–43
BW
Bandwidth (3 dB)
90
MHz
E_glitch
Glitch energy
Full-scale code transition at 205 MSPS
25
pVs
(9) This value excludes the digital process delay, t_D(D). Limit from characterization only. Data is clocked in on the rising edge of CLKIN.
Analog outputs become available on the falling edge of CLKIN.
(10) Limit from characterization only.
7.4 Power Requirements
7.4.1 Power for 700-mV DAC Output Compliance + 350-mV Bias at AVDD = 3.3 V,
DVDD = 1.8 V, VDD_IO = 3.3 V, VDD_DLL = 3.3 V, 1-MHz Tone on All Channels
f (MHz)
20
30
80
160
200
POWER (mW),
DLL BYPASSED
329.91
338.52
382.47
450.51
476.01
POWER (mW),
DLL USED
332.88
351.72
399.63
IAVDD (mA)
93.2
93.2
93.2
93.2
93.2
IDVDD (mA)
10.4
15
38.5
75.2
89
IVDD_IO (mA)
1.1
1.2
1.7
2.3
2.5
IVDD_DLL (mA)
0.9
4
5.2
500
400
DLL Used
300
DLL
Bypassed
200
100 _{V = 700 mV}
VIO = 3.3 V
V(BIAS) = 350 mV
0
20
30
80
160
200
f - Frequency - MHz
Figure 7-1. POWER vs FREQUENCY
7.4.2 Power for 700-mV DAC Output Compliance + 350-mV Bias at AVDD = 3.3 V,
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Electrical Characteristics
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