THS8200IPFP Datasheet, PDF (15/104 Pages) Texas Instruments – All-Format Oversampled Component Video/PC Graphics D/A System

THS8200-EP
www.ti.com
SLES253 – DECEMBER 2009
3.1 Data Manager (DMAN)
The data manager is the block that transforms the selected input video data format present on the chip
input bus(es) to an internal 10-bit three-channel representation. Supported input formats include 10-/8-bit
ITU-R.BT656 with embedded sync codes, 15-/16- or 24-/30-bit RGB with external sync, 20-/16-bit
SMPTE274M/296M with embedded sync codes, as well as 20-/16-bit YCbCr 4:2:2 with external sync. The
user can optionally include a 4:2:2 to 4:4:4 interpolation on the color data path. When a format with
embedded sync is selected, DMAN also extracts H(Hsync), V(Vsync), F(FieldID) identifiers from the
ITU-R.BT656 (SDTV) or SMPTE274M/296M (HDTV) data stream for internal synchronization of the DTG.
Alternatively, the device synchronizes to HS_IN, VS_IN, FID inputs.
3.1.1 Interpolating Finite Impulse Responses Filter (IFIR)
The interpolating FIR is used to upsample the input data by 2×. In the THS82000 there are five IFIRs. The
first two are used only when the input data is in 4:2:2 format for conversion to a 4:4:4 internal
representation on both color difference channels. The last three IFIRs are used to upsample the internal
data to the DACs on all three channels in case 2× video interpolation is enabled. By 2× oversampling the
video data, the requirements for the analog reconstruction filter at the DAC outputs are relaxed so it can
be built with fewer components, thereby also improving the overall video frequency characteristic (less
group delay variation). All of the IFIRs can be bypassed or switched in by programming the appropriate
I²C registers. The coefficients of all IFIRs are fixed.
3.1.2 Color-Space Conversion (CSC)
The color-space converter block is used to convert input video data in one type of color space to output
video data in another color space (e.g., RGB to YCbCr, or vice versa). This block contains a 3×3 matrix
multiplier/adder and a 3×1 adder. All multiplier and adder coefficients can be programmed via the I²C
interface to support any linear matrixing+offset operation on the video data.
3.1.3 Clip/Shift/Multiplier (CSM)
The clip-shift-multiply block optionally clips the input code range at a programmed low/high code, shifts the
input video data downwards, and multiplies the input by a programmable coefficient in the range 0−1.999.
This allows for operation with a reduced input code range such as prescribed in the ITU-R.BT601
recommendation. Each channel can be independently programmed to accommodate different digital
ranges for each of the three input channels. For example, for standard video signals the Y channel has a
digital input range of 64−940, whereas the two other channels have an input range of 64−960. All three
channels must have a DAC output range of 0−700 mV, so normally the analog voltage corresponding to 1
LSB would have to change to account for the different digital inputs. This might cause matching errors.
Therefore in the THS8200 the DAC LSB does not change; rather LSB conversion is done by scaling the
digital inputs to the DAC’s full input range. Furthermore, the CSM output is 11 bits wide and is sent to the
11-bit DACs. The extra bit of resolution resolves nonlinearities introduced by the scaling process. The
clipping function can be switched off to allow for super-white/super-black excursions.
3.1.4 Digital Multiplexer (DIGMUX)
This multiplexer in front of the DACs can select between video signals at 1× or 2× the pixel clock rate. It is
also used to switch in blanking/sync level data generated by the display timing generator (DTG) block and
test pattern data (e.g., color bars, I²C-controlled DAC levels) or to perform data insertion (CGMS) during
vertical blanking.
Copyright © 2009, Texas Instruments Incorporated
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THS8200 Functional Overview
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