THS8200IPFP Datasheet, PDF (66/104 Pages) Texas Instruments – All-Format Oversampled Component Video/PC Graphics D/A System

THS8200-EP
SLES253 – DECEMBER 2009
www.ti.com
REGISTER
NAME
R/W
dtg2_vs_in
_dly_lsb
R/W
dtg2_pixel_
cnt_msb
R
dtg2_pixel_
cnt_lsb
R
dtg2_line_
cnt_msb
R
dtg2_line_
cnt_msb
R
dtg2_cntl R/W
cgms_cntl_
header
R/W
cgms_payload
_ msb
R/W
cgms_payload
_ lsb
R/W
misc_ppl_ lsb R
misc_ppl_ msb R
misc_lpf_ lsb R
misc_lpf_ msb R
SUB-
ADDRESS
BIT7
BIT6
0x7c
dtg2_vs_in_dly(7:0)
BIT5
BIT4
BIT3
0x7d
dtg2_pixel_cnt(15:8)
0x7e
0x7f
0x80
0x81
0x82
0x83
dtg2_pixel_cnt(7:0)
dtg2_ip_
fmt
Reserved
dtg2_line_cnt(7:0)
Reserved
dtg2_fid_
de_cntl
dtg2_rgb_
mode_on
dtg2_emb
edded_
timing
dtg2_
vsout_pol
CGMS CONTROL
dtg2_h
sout_pol
Reserved cgms_en cgms_header(5:0)
0x84
Reserved Reserved cgms_payload(13:8)
0x85
0x86
0x87
0x88
0x89
cgms_payload(7:0)
misc_ppl(7:0)
misc_ppl(7:0)
misc_lpf(7:0)
misc_lpf(15:8)
BIT2
BIT1
BIT0
dtg2_line_cnt(10:8)
dtg2_fid_ dtg2_vs_ dtg2_hs_
pol
pol
pol
5.1 Register Descriptions
Between { } are shown the name(s), subaddress(es) and bit position(s) where each register can be found
in the register map.
The default register value is shown between [ ] in binary format, and hexadecimal (h) and/or decimal (d)
notation where listed.
5.1.1 System Control (Sub-Addresses 0x02−0x03)
ver(7:0):
Device version
{version 0x02(7..0)}
[0000 0000]
The user can read this register to find out which version of THS8200 is in the system.
vesa_clk:
Clock mode selection
{chip_ctl 0x03(7)}
[0]
0 : Normal operation
1 : All clocks become identical, except for the half-rate clock, and the DLL is bypassed. This is used
in VESA mode to support a direct 205-MHz input clock. No internal 2× interpolation is available. This
mode should be used for all formats that require a >80 MSPS pixel clock because the internal DLL
for 2× clock generation is specified only up to 80 MSPS.
The half-rate clock is still internally generated if needed to allow, e.g., 148-MHz 20-bit input (1080P).
dll_bypass:
{chip_ctl 0x03(6)}
DLL bypass
[0]
66
I²C Register Map
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