THS8200IPFP Datasheet, PDF (16/104 Pages) Texas Instruments – All-Format Oversampled Component Video/PC Graphics D/A System

THS8200-EP
SLES253 – DECEMBER 2009
www.ti.com
3.1.5 Display Timing Generator (DTG)
The display timing generator is responsible for the generation of the correct frame format including all
sync, equalization and serration pulses. In master timing mode, the DTG is synchronized to external
synchronization inputs, either from the dedicated device terminals HS_IN, VS_IN, and FID or is
synchronized to the identifiers extracted from the input data stream, as selected by the DMAN mode. In
master timing mode, the DTG generates the required field/frame format based on the externally applied
pixel clock input.
When active data is not being passed to the DACs, i.e., during the horizontal/vertical blanking intervals,
the DTG generates the correct digital words for blank, sync levels and other level excursions, such as pre-
and post-serration pulses and equalization pulses.
Horizontal timings, as well as amplitudes of negative and positive sync, HDTV broad pulses and SDTV
pre- and post-equalization and serration pulses, are all I²C-programmable to accommodate, e.g., the
generation of both EIA.770-1 (10:4 video/sync ratio) and EIA.770-2 (7:3 video/sync ratio) compliant analog
component video outputs, and to support nonstandard video timing formats.
In addition or as an alternative to the composite sync inserted on green/luma channel or all analog
outputs, output video timing can be carried via dedicated Hsync/Vsync output signals as well. The
position, duration and polarity of Hsync and Vsync outputs are fully programmable in order to support, for
example, the centering of the active video window within the picture frame.
The DTG also controls the data multiplexer in the DIGMUX block. DIGMUX can be programmed to pass
device input data only on active video lines (inserting DTG-generated blanking level during blanking
intervals). Alternatively, the DTG can pass device input data also during some VBI lines (ancillary data in
the input stream is passed transparently on some VBI lines). Finally, the device can also generate its own
ancillary data and insert it into the analog outputs according to the CGMS data format for the 525P video
format.
3.1.6 Clock Generator (CGEN)
The clock generator is an analog delay-locked loop (DLL) based circuit and provides a 2× clock from the
CLKIN input. The 2× clock is used by the CDRV block for 2× video interpolation. Some video formats also
require a 1/2 rate clock used for 4:2:2 to 4:4:4 conversion.
3.1.7 Clock Driver (CDRV)
The clock drive block generates all on-chip clocks. Its inputs are control signals from the digital logic, the
original CLKIN, and the 2× clock from CGEN. Outputs include a half-rate clock, full-rate clock, and a 2×
full-rate clock. The clocks are used for both optional on-chip interpolation processes: 4:2:2 to 4:4:4
interpolation and 1× to 2× video oversampling.
3.1.8 I²C Host Interface (I2CSLAVE)
The I²C interface controls and programs the internal I²C registers. The THS8200 I²C interface
implementation supports the fast I²C specification (SCL: 400 kHz) and allows the writing and reading of
registers. An auto-increment addressing feature simplifies block register programming. The I²C interface
works without a clock present on CLKIN.
3.1.9 Test Block (TST)
The test block controls all the test functions of the THS8200. In addition to manufacturing test modes, this
block contains several user test modes including a DAC internal ramp generator and a 75% SMPTE video
color bar generator.
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THS8200 Functional Overview
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