THS8200IPFP Datasheet, PDF(80/104 Page) Texas Instruments – All-Format Oversampled Component Video/PC Graphics D/A System

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THS8200IPFP Datasheet, PDF (80/104 Pages) Texas Instruments – All-Format Oversampled Component Video/PC Graphics D/A System

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THS8200-EP

SLES253 â DECEMBER 2009

www.ti.com

{dtg2_vlength1_msb_vdly1_msb

0x74(2:0)

and dtg2_vdly1_lsb 0x75(7:0)}

[000 0000 0011]

Sets the line number that the VS_OUT signal is asserted on for progressive video modes or for field

1 of interlaced video modes.

Note: when programmed to a value higher than the total number of lines per frame, there is no

VS_OUT output.

dtg2_vlength2(9:0):

VS_OUT duration, field 2

{dtg2_vlength2_msb_vdly2_msb

0x77(7:6)

and dtg2_vlength2_lsb 0x76(7:0)}

[00 0000 0000]

Sets the duration of the VS_OUT output signal during the vertical blank interval of field 2 in

interlaced video modes. In progressive video modes, this register must be set to all 0.

dtg2_vdly2(10:0):

VS_OUT delay, field 2

{dtg2_vlength2_msb_vdly2_msb

0x77(2:0)

and dtg2_vdly2_lsb 0x78(7:0)}

[111 1111 1111]

Sets the line number that the VS_OUT signal is asserted on for field 2 of interlaced scan video

modes. For progressive scan video modes, this register must be set to all 1.

dtg2_hs_in_dly(12:0):

DTG horizontal delay

{dtg2_hs_in_dly_msb 0x79(4:0)

and

dtg2_hs_in_dly_lsb 0x7A(7:0)}

[0 0000 0011 1101]

Sets the number of pixels that the DTG startup is horizontally delayed with respect to HS input for

dedicated timing modes or EAV input for embedded timing modes.

Note: It is possible to delay startup past the end of a line when this delay is programmed higher than

the total number of pixels per line.

dtg2_vs_in_dly(10:0):

DTG vertical delay

{dtg2_vs_in_dly_msb 0x7B(2:0)

and

dtg2_vs_in_dly_lsb 0x7C(7:0)}

[000 0000 0011]

Sets the number of lines that the DTG startup is vertically delayed with respect to VS input for

dedicated timing modes or the line counter value for embedded timing.

Note: It is possible to delay startup past the end of a frame when this delay is programmed higher

than the total number of lines per frame.

dtg2_pixel_cnt(15:0):

Pixel count readback

{dtg2_pixel_cnt_msb 0x7D(7:0) and

dtg2_pixel_cnt_lsb 0x7E(7:0)}

Reports the number of clock 1x rising edges between consecutive Hsync input pulses

dtg2_ip_fmt:

Interlaced/progressive-scan indicator

{dtg2_line_cnt_msb 0x7F(7)}

Indicates whether current video frame is progressive (0) or interlaced (1)

I2C Register Map

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