THS8200IPFP Datasheet, PDF (62/104 Pages) Texas Instruments – All-Format Oversampled Component Video/PC Graphics D/A System

THS8200-EP
SLES253 – DECEMBER 2009
www.ti.com
5 I²C Register Map
R/W registers can be written and read.
R registers are read-only.
REGISTER
NAME
R/W
SUB-
ADDRESS
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
0x00
0x01
Reserved
SYSTEM
version
R
0x02
ver7
ver6
ver5
ver4
ver3
ver2
ver1
ver0
chip_ctl
R/W
0x03
vesa_clk
dll_bypass
vesa_color
bars
dll_freq_
sel
dac_pwdn chip_pwdn
chip_ms
arst_
func_n
COLOR SPACE CONVERSION
csc_r11
R/W
0x04
csc_ric1(5:0)
csc_rfc1(9:8)
csc_r12
R/W
0x05
csc_rfc1(7:0)
csc_r21
R/W
0x06
csc_ric2(5:0)
csc_rfc2(9:8)
csc_r22
R/W
0x07
csc_rfc2(7:0)
csc_r31
R/W
0x08
csc_ric3(5:0)
csc_rfc3(9:8)
csc_r32
R/W
0x09
csc_rfc3(7:0)
csc_g11 R/W
0x0a
csc_gic1(5:0)
csc_gfc1(9:8)
csc_g12 R/W
0x0b
csc_gfc1(7:0)
csc_g21 R/W
0x0c
csc_gic2(5:0)
csc_gfc2(9:8)
csc_g22 R/W
0x0d
csc_gfc2(7:0)
csc_g31 R/W
0x0e
csc_gic3(5:0)
csc_gfc3(9:8)
csc_g32 R/W
0x0f
csc_gfc3(7:0)
csc_b11 R/W
0x10
csc_bic1(5:0)
csc_bfc1(9:8)
csc_b12 R/W
0x11
csc_bfc1(7:0)
csc_b21 R/W
0x12
csc_bic2(5:0)
csc_bfc2(9:8)
csc_b22 R/W
0x13
csc_bfc2(7:0)
csc_b31 R/W
0x14
csc_bic3(5:0)
csc_bfc3(9:8)
csc_b32 R/W
0x15
csc_bfc3(7:0)
csc_offs1 R/W
0x16
csc_offset1(9:2)
csc_offs12 R/W
0x17
csc_offset1(1:0)
csc_offset2(9:4)
csc_offs23 R/W
0x18
csc_offset2(3:0)
csc_offset3(9:6)
csc_offs3 R/W
0x19
csc_offset3(5:0)
csc_
bypass
c_uof_cnt l
TEST
tst_cntl1 R/W
0x1a
st_
digbpass
tst_offset
Reserved
tst_cntl2 R/W
0x1b
tst_ydelay(1:0)
Reserved
Reserved
Reserved
Reserved
tst_
fastramp
tst_
slowramp
DATA PATH
data_cntl R/W
0x1c
data_
clk6 56_on
data_fsadj
data_ifir12
_bypass
data_ifir35
_bypass
data_
tristate656
data_dman_cntl(2:0)
DISPLAY TIMING GENERATION, PART 1
dtg1_y_
sync1_lsb
R/W
0x1d
dtg1_y_blank(7:0)
dtg1_y_
sync2_lsb
R/W
0x1e
dtg1_y_sync_low(7:0)
dtg1_y_
sync3_lsb
R/W
0x1f
dtg1_y_sync_high(7:0)
62
I²C Register Map
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