THS8200IPFP Datasheet, PDF (35/104 Pages) Texas Instruments – All-Format Oversampled Component Video/PC Graphics D/A System

THS8200-EP
www.ti.com
SLES253 – DECEMBER 2009
• Output synchronization: The available set of output synchronization line types depends on these
modes. The user can choose from a number of predefined line types for each mode. In each mode,
the user is able to program the timings along the line. However some timings are hard coded by the
selected DTG_mode (e.g., rise/fall times for sync are different; see DTG Line Type Overview, Section
4.7.3) and not all line types can be selected in each DTG mode (e.g., HDTV allows tri-level sync, while
SDTV only allows generation of bi-level negative syncs).
4.7.2.1 Predefined DTG Video Formats (Presets)
While the DTG has the flexibility to generate a wide array of video output formats and their
synchronization signals, the most common video formats have predefined settings for the field and frame
sizes and for (line type, breakpoint) settings.
When selecting a video format preset, the horizontal timings of the line types still need to be programmed.
The preset only fixes the (line type, breakpoint) table.
4.7.2.2 Internal Synchronization
The pixel and line counters of the DTG are reset by internal signals. In slave mode (THS8200 slaves to
external video input source) these signals are derived from either the embedded SAV/EAV codes or the
dedicated Hsync/Vsync/FID inputs. In master mode, these counters are in free-run and the HS_IN/VS_IN
signals are generated by the THS8200 based on the programmed field/frame parameters. Master mode is
only available for progressive-scan VESA modes. FID is not generated in master mode.
The user can delay, in both horizontal and vertical directions, the 0-reference of the DTG by programming
the input delay registers. Physically, the horizontal and vertical DTG startup values are altered. The effect
is that, when a vertical or horizontal sync is received, either from dedicated inputs or from embedded
SAV/EAV codes, the output frame starts at position (x,y). This ensures that, for example, the output video
frame can be centered on the display.
Based on the 0-reference of the DTG, the line types are generated and the DIGMUX will select between
the video input and the DTG output for each line type. All horizontal timings of the different line types are
programmable, including the portion of the video line seen as active video. A complete overview of all
available line types in either SDTV or HDTV mode is presented in Section 4.7.3.
Additionally, Hsync/Vsync outputs can be generated, synchronized to the THS8200 DAC outputs. These
outputs are programmable in width, position and polarity, based on the horizontal/vertical pixel counters,
and thus independently of the DTG reference. This ensures that independent synchronization is possible
between the composite sync output inserted into the DAC output(s) and the dedicated Hsync/Vsync
outputs. Because of their programmability, these output signals could be used for other purposes as well;
e.g., Vsync could be programmed as a signal active during the VBI.
Figure 4-15 shows how the internal pixel and line counters are synchronized to internal HS and VS signals
in slave mode. HS and VS are internal signals derived from either HS_IN, VS_IN, or from embedded
SAV/EAV codes in the input video data. Since the 0-reference of the DTG is determined by these
counters, the dtg2_vs_in_dly and dtg2_hs_in_dly register settings influence both HS_OUT, VS_OUT and
composite sync output timing. The dtg2_vdly<1,2> and dtg2_hdly settings, on the other hand, only affect
HS_OUT and VS_OUT, because they are downstream of the pixel counter. Likewise, dtg2_hlength and
dtg2_vlength<1,2> only affect these dedicated sync output signals.
Copyright © 2009, Texas Instruments Incorporated
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Detailed Functional Description
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