THS8200IPFP Datasheet, PDF (72/104 Pages) Texas Instruments – All-Format Oversampled Component Video/PC Graphics D/A System

THS8200-EP
SLES253 – DECEMBER 2009
www.ti.com
data_dman_cntl(2:0): Data manager control
{data_cntl 0x1C(2:0)} [011]
Selects the format for the input data manager, as follows:
dman_cntl
000
001
010
011
100
Others
MODE
30-bit YCbCr/RGB 4:4:4
16-bit RGB 4:4:4
15-bit RGB 4:4:4
20-bit YCbCr 4:2:2
10-bit YCbCr 4:2:2 (ITU mode)
(Reserved)
5.1.5 Display Timing Generator Control, Part 1 (Sub-Addresses 0x1D−0x3C)
dtg1_y_blank(9:0):
Y channel blanking level amplitude control
{dtg1_y_sync_msb 0x23(5:4) and [10 0000 0000]
dtg1_y_sync1_lsb 0x1D(7:0)}
Sets the amplitude of the blanking level for the Y channel
dtg1_y_sync_low(9:0):
Y channel low sync level amplitude control
{dtg1_y_sync_msb 0x23(3:2) and [00 0000 0000]
dtg1_y_sync2_lsb 0x1E(7:0)}
Sets the amplitude of the negative sync and equalization/serration/broad pulses for the Y channel
dtg1_y_sync_high(9:0):
Y channel high sync level amplitude control
{dtg1_y_sync_msb 0x23(1:0) and [11 0000 0000]
dtg1_y_sync3_lsb 0x1F(7:0)}
Sets the amplitude of the positive sync for the Y channel
dtg1_cbcr_blank(9:0):
Cb/Cr channel blanking level amplitude control
{dtg1_cbcr_sync_msb 0x24(5:4)
and
dtg1_cbcr_sync1_lsb 0x20(7:0)}
[10 0000 0000]
Sets the amplitude of the blanking level for the Cb and Cr channels
dtg1_cbcr_sync_low (9:0):
Cb/Cr channel low sync level amplitude control
{dtg1_cbcr_sync_msb 0x24(3:2)
and
dtg1_cbcr_sync2_lsb 0x21(7:0)}
[00 0000 0000]
Sets the amplitude of the negative sync and equalization/serration/broad pulses for the Cb and Cr
channels
dtg1_cbcr_sync_high(9:0):
Cb/Cr channel high sync level amplitude control
{dtg1_cbcr_sync_msb 0x24(1:0)
and
dtg1_cbcr_sync3_lsb 0x22(7:0)}
[11 0000 0000]
Sets the amplitude of the positive sync for the Cb and Cr channels
dtg1_spec_a(7:0):
{dtg1_spec_a 0x25(7:0)}
Negative HSync width
[0010 1100] = [44d]
72
I²C Register Map
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