THS8200IPFP Datasheet, PDF (3/104 Pages) Texas Instruments – All-Format Oversampled Component Video/PC Graphics D/A System

THS8200-EP
www.ti.com
SLES253 – DECEMBER 2009
4.7.3.9 SDTV Mode ......................................................................................... 45
4.7.3.10 NEQ_NEQ (Negative Equalization Pulse/Negative Equalization Pulse) .................... 47
4.7.3.11 FULL_BSP (Full Broad Sync Pulse) ............................................................. 47
4.7.3.12 BSP_BSP (Broad Sync Pulse/Broad Sync Pulse) ............................................. 48
4.7.3.13 FULL_NSP (Full Normal Sync Pulse) ........................................................... 48
4.7.3.14 NEQ_BSP (Negative Equalization Pulse/Broad Sync Pulse) ................................ 49
4.7.3.15 BSP_NEQ (Broad Sync Pulse/Negative Equalization Pulse) ................................ 49
4.7.3.16 FULL_NEQ (Full Negative Equalization Pulse) ................................................ 50
4.7.3.17 NSP_ACTIVE (Normal Sync Pulse/Active Video) ............................................. 50
4.7.3.18 ACTIVE_NEQ (Active Video/Negative Equalization Pulse) .................................. 51
4.7.3.19 ACTIVE VIDEO ..................................................................................... 51
4.8 D/A Conversion ............................................................................................................ 53
4.8.1 RGB Output Without Sync Signal Insertion/General-Purpose Application DAC ....................... 54
4.8.2 SMPTE-Compatible RGB Output With Sync Signal Inserted on G (Green) Channel ................. 55
4.8.3 SMPTE-Compatible Analog-Level Output With Sync Inserted on All RGB Channels ................. 56
4.8.4 SMPTE-Compatible YPbPr Output With Sync Signal Inserted on Y Channel Only ................... 57
4.8.5 SMPTE-Compatible YPbPr Output With Sync Signal Inserted on All Channels ....................... 58
4.8.6 Summary of Supported Video Formats ...................................................................... 59
4.9 Test Functions ............................................................................................................. 59
4.10 Power Down ................................................................................................................ 59
4.11 CGMS Insertion ............................................................................................................ 59
4.12 I²C Interface ................................................................................................................ 60
5 I²C Register Map ................................................................................................................ 62
5.1 Register Descriptions ..................................................................................................... 66
5.1.1 System Control (Sub-Addresses 0x02−0x03) .............................................................. 66
5.1.2 Color Space Conversion Control (Sub-Addresses 0x04−0x19) .......................................... 68
5.1.3 Test Control (Sub-Addresses 0x1A−0x1B) .................................................................. 70
5.1.4 Data Path Control (Sub-Address 0x1C) ..................................................................... 71
5.1.5 Display Timing Generator Control, Part 1 (Sub-Addresses 0x1D−0x3C) ............................... 72
5.1.6 DAC Control (Sub-Addresses 0x3D−0x40) ................................................................. 75
5.1.7 Clip/Scale/Multiplier Control (Sub-Addresses 0x41−0x4F) ................................................ 76
5.1.8 Display Timing Generator Control, Part 2 (Sub-Addresses 0x50−0x82) ................................ 79
5.1.9 CGMS Control (Sub-Addresses 0x83−0x85) ............................................................... 82
5.2 THS8200 Preset Mode Line Type Definitions ......................................................................... 82
5.2.1 SMPTE_274P (1080P) ......................................................................................... 82
5.2.2 274M Interlaced (1080I) ....................................................................................... 83
5.2.3 296M Progressive (720P) ..................................................................................... 83
5.2.4 SDTV 525 Interlaced Mode ................................................................................... 83
5.2.5 SDTV 525 Progressive Mode ................................................................................. 84
5.2.6 SDTV 625 Interlaced Mode ................................................................................... 84
6 Application Information ...................................................................................................... 85
6.1 Video vs Computer Graphics Application .............................................................................. 85
6.2 DVI to Analog YPbPr/RGB Application ................................................................................. 85
6.3 Master vs Slave Timing Modes .......................................................................................... 86
7 Electrical Characteristics .................................................................................................... 88
7.1 Absolute Maximum Ratings .............................................................................................. 88
Copyright © 2009, Texas Instruments Incorporated
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