THS8200IPFP Datasheet, PDF (12/104 Pages) Texas Instruments – All-Format Oversampled Component Video/PC Graphics D/A System

THS8200-EP
SLES253 – DECEMBER 2009
TERMINAL
NAME
NO.
ABPb
15
ARPr
17
AG Y
13
AVDD
AVSS
11, 14, 18
12, 16
BCb[9:0]
21 - 30
CLKIN
COMP1
COMP2
D1CLKO
DO[9:5]
DO[4:0]
DVDD
DVSS
FID
3
10
9
71
65 - 69
73 - 77
32, 59, 79
31, 58, 78
47
FSADJ1
7
FSADJ2
GND_DLL
GND_IO
GY[9:0]
8
2
20, 45, 72
48 - 57
HS_IN
43
HS_OUT
12CA
N.C.
PBKG (VSS)
61
5
1, 80
6
RCr[9:0]
33 - 42
RESETB
60
Table 2-1. TERMINAL FUNCTIONS
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I/O ⁽¹⁾
O
O
O
PWR
PWR
I
I
P
P
O
O
PWR
PWR
I
P
P
PWR
PWR
I
I/O
O
I
I
PWR
I
I
DESCRIPTION
Analog output of DAC2. See AGY.
Analog output of DAC3. See AGY.
Analog output of DAC1. With the proper setting of FSADJ<n>, this output is capable of
driving 1.3-V full scale into a 37.5-Ω load.
Analog power supply, nominal 3.3 V
Analog ground
10-bit video data input port. All 10 bits or the 8 MSB of this port can be connected to the
video data source. In 30-bit mode, the B data of RGB, or the Cb data of YCbCr, should be
connected to this port. In 10-bit input mode, this port is unused. In 20-bit input mode, this
port is used for CbCr input data.
Main clock input. Video input data on the GY[9:0]/BCb[9:0]/RCr[9:0] ports should be
synchronized to CLKIN. Depending on the input data format, CLKIN is supplied to THS8200
at 1x or 2x the pixel clock frequency.
Compensation pin for the internal reference amplifier. A 0.1-μF capacitor should be
connected between COMP1 and analog power supply AVDD.
Compensation pin for the internal reference amplifier. A 0.1-μF capacitor should be
connected between COMP2 and analog power supply AVDD.
Video ITU-R.BT656-compliant clock output. This clock output is off by default and should be
activated via an I²C register setting.
ITU-R.BT656 compliant video data output port. Only available when ITU-R.BT656 input
format is used. Can be used to connect to external PAL/NTSC video encoder. This port is off
by default and should be activated via an I²C register setting.
Digital core power, nominal 1.8 V
Digital core ground
Field identification signal for interlaced video formats. In slave timing mode, this is an input
from the video data source. In master timing mode this signal is unused, as only
progressive-scan VESA formats are supported in master mode.
Full scale adjustment control 1. A resistor should be connected between FSADJ1 and analog
ground AGND to control the full-scale output current of the DAC output channels. Via the
data_fsadj I²C programming register, the user can select between two full-scale ranges,
determined by FSADJ1 or FSADJ2.
For 700-mV video output (1 Vpp including sync), the nominal value is 2.99 kΩ ; for 1.0-Vpp
video output (1.3 Vpp including sync) output the nominal value is 2.08 kΩ.
Full scale adjustment control 2. See FSADJ1.
Ground of clock doubler. Should be connected to analog ground.
I/O ring ground
10-bit video data input port. All 10 bits or the 8 MSB of this port can be connected to the
video data source. The G data of RGB or the Y data of YCbCr should be connected to this
port. Port used in 10-bit mode for CbYCrY video input data; in 20-bit input mode for Y data.
Horizontal source synchronization. In slave timing mode, this is an input from the video data
source. In master timing mode, this is an output to the video data source with programmable
timing and polarity, serving as a horizontal data qualification signal to the video source.
Horizontal sync output (to display). Irrespective of slave/master timing mode configuration,
this is always an output with timing generated by the DTG.
I²C device address LSB selection
Manufacturing test input. Must be tied to GND for normal operation.
Substrate ground. Should be connected to analog ground.
10-bit video data input port. All 10-bits or the 8 MSB of this port can be connected to the
video data source. In 30-bit mode, the R data of RGB or the Cr data of YCbCr should be
connected to this port. In the 10- /20-bit input mode, this port is unused. For some input
formats this port is unused.
Software reset pin (active low). The minimum reset duration is 200 ns.
(1) I = input, O = output, B = bidirectional, PWR = power or ground, P = passive
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