THS8200IPFP Datasheet, PDF (13/104 Pages) Texas Instruments – All-Format Oversampled Component Video/PC Graphics D/A System

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TERMINAL
NAME
NO.
SCL
64
SDA
VDD_DLL
VDD_IO
63
4
19, 46, 70
VS_IN
44
VS_OUT
62
THS8200-EP
I/O ⁽¹⁾
B
B
PWR
PWR
I/O
O
SLES253 – DECEMBER 2009
TERMINAL FUNCTIONS (continued)
DESCRIPTION
Serial clock line of I²C bus interface. Open-collector. Maximum specified clock speed is
400 kHz (fast I²C).
Serial data line of I²C bus interface. Open-collector.
Power supply of clock doubler, nominal 1.8 V
I/O ring power, 1.8 V or 3.3 V nominal
Vertical source synchronization. In slave timing mode, this is an input from the video data
source. In master timing mode, this is an output to the video data source with programmable
timing and polarity, serving as a vertical data qualification signal to the video source.
Vertical sync output (to display). Irrespective of slave/master timing mode configuration, this
is always an output with timing generated by the DTG.
Copyright © 2009, Texas Instruments Incorporated
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