THS8200IPFP Datasheet, PDF (34/104 Pages) Texas Instruments – All-Format Oversampled Component Video/PC Graphics D/A System

THS8200-EP
SLES253 – DECEMBER 2009
www.ti.com
4.7.2 Functional Description
The user should program the DTG with the correct parameters for the current video format. The DTG
contains a line and a pixel counter, and a state machine to determine which user−defined line waveform to
output for each line on the analog outputs. The pixel counter counts horizontally up to the total number of
pixels per line, programmed in ‘dtg1_total_pixels’. The line counter counts up to ‘dtg1_field_size’ lines in
the first field, and continues its count up to ‘dtg1_frame_size’ lines in the total frame (field1+field2).
The current field is derived from the even/odd field ID signal, which is sampled at the start of the Vsync
period. The source for the internal FID signal can be either the signal to the FID terminal, or can be
internally derived from relative Hsync/Vsync alignment on the corresponding terminals, as selected by
‘dtg2_fid_de_cntl’ and the current DTG mode (VESA vs. SDTV/HDTV). See register map description of
‘dtg2_fid_de_cntl’ for more details. Derivation of FID from Hsync/Vsync input alignment is done according
to the EIA−861 specification. There is a tolerance implemented on Hsync/Vsync transition misalignment.
When the active edge of the Vsync transition occurs within ±63 clock cycles from the active edge of
Hsync, both signals are interpreted as aligned, which signals field 1. Because of this timing window, the
internal FieldID signal is generated later than the start of Vsync period. Since the signal is internally
sampled at the start of the Vsync period to determine the current field, the field interpretation is opposite.
Use the ‘field_flip’ register to correct this through field reversal.
If the video format is progressive, only field1 exists and no FID signal is needed. However the DTG will
only startup when a field 1 condition is detected i.e when FID is detected low at the start of the Vsync
period. Thus in the case of a progressive video format, and when using the device with external FID input,
the user must make sure to keep the FID terminal low.
It is also needed for proper DTG synchronization that the programmed Hsync and Vsync input polarities
are correct. Since Hsync, Vsync polarities change for different VESA PC formats, the device has built−in
support to detect the incoming sync polarities. This is done by comparing the width of Hsync high
(‘misc_ppl’) to the total line length (‘dtg2_pixel_cnt’) to derive the Hsync duty cycle and thus its polarity.
Upon this detection, the user can program the detected incoming polarity for DTG input synchronization
(‘dtg2_hs_pol’) – it is not set automatically by the device. The procedure is similar for Vsync polarity
detection, using registers ‘misc_lpf’, ‘dtg2_line_cnt’ and ‘dtg2_vs_pol’.
The DTG synchronization can be separated into three functions:
• Internal synchronization: How the DTG is synchronized with respect to the internal horizontal and
vertical counters.
• Source synchronization: How the horizontal and vertical counters are synchronized to the
HS_IN/VS_IN/FID or SAV/EAV signals.
• Output synchronization: how the output timings HS_OUT, VS_OUT, and the composite sync output
are synchronized to the DTG and the horizontal and vertical counters.
The DTG is based on a state machine that can generate a set of line types which can override the values
on the DAC inputs. The DTG output is multiplexed into the data path by the DIGMUX. The selected video
format preset setting, or the programmed (line type, breakpoint) table in case a generic mode is selected
in dtg1_mode, determines which line type is generated for a particular line, and where this DTG output is
used to override the normal DAC inputs. Internally, a fixed preconfigured number of line types exists from
which the user can select.
Also, for each set of line types (we will see next there are two different sets of line types possible) the user
can program the horizontal duration of each predefined excursion (negative sync, positive sync, back
porch, front porch, broad pulse, interlaced sync, etc.) and also the amplitude (e.g., negative sync
amplitude, positive sync amplitude, blank amplitude).
The setting of dtg1_mode determines:
• Internal synchronization: The 0H reference (horizontal reset of the DTG) is different between SDTV
and HDTV.
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Detailed Functional Description
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