DRV8305-Q1_16 Datasheet, PDF (7/54 Pages) Texas Instruments – Three-Phase Automotive Gate Driver

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DRV8305-Q1
SLVSD12A – MAY 2015 – REVISED MARCH 2016
6.5 Electrical Characteristics
PVDD = 4.4 to 45 V, DRV8305xQ: T_J = –40°C to 150°C, DRV8305xE: T_J = –40°C to 175°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SUPPLIES (PVDD, DVDD, AVDD)
4.4
V_PVDD
PVDD operating voltage
Voltage regulator (VREG) operational
4.3
45
V
45
I_{PVDD_Operating}
PVDD operating supply
current
EN_GATE = HIGH; VREG no load;
outputs HI-Z
20
mA
I_{PVDD_Standby}
PVDD standby supply
current
EN_GATE = LOW; VREG no load
5
mA
I_{PVDD_Sleep}
V_AVDD
PVDD sleep supply current
Internal regulator voltage
EN_GATE = LOW; Sleep Mode;
T_J = –40 to 150 °C
EN_GATE = LOW; Sleep Mode;
T_J = 150 to 175 °C
PVDD = 5.3 to 45 V
PVDD = 4.4 to 5.3 V
60
4.85
PVDD – 0.4
5
PVDD
200 μA
250 uA
5.15
V
V_DVDD
Internal regulator voltage
VOLTAGE REGULATOR (3.3-V or 5-V VREG)
3.3
V
PVDD = 5.4 to 45 V
VREG ×
0.97
VREG
VREG ×
1.03
V_VREG
VREG DC output voltage
PVDD = 4.4 to 5.3 V; 5-V regulator
PVDD = 4.4 to 5.3 V; 3.3-V regulator
PVDD – 0.4
VREG ×
0.97
VREG
PVDD V
VREG ×
1.03
V_LineReg
Line regulation ΔV_OUT/ΔV_IN 5.3 V ≤ V_IN ≤ 12 V; I_O = 1 mA
V_LoadReg
Load regulation
ΔV_OUT/ΔI_OUT
100 μA ≤ I_OUT ≤ 50 mA
V_do
Dropout voltage
I_OUT = 100 μA; 3.3 V
I_OUT = 50 mA; 3.3 V
LOGIC-LEVEL INPUTS (INHx, INLx, EN_GATE, SCLK, nSCS)
10
30 mV
30 mV
0.05
0.1
V
0.2
0.4
V_IL
Input logic low voltage
V_IH
Input logic high voltage
R_PD
Internal pulldown resistor To GND
CONTROL OUTPUTS (nFAULT, SDO, PWRGD)
0
2
100
0.8 V
5V
kΩ
V_OL
Output logic low voltage
nFAULT; SDO; PWRGD; I_O = 5 mA
V_OH
Output logic high voltage
SDO; I_O = 5 mA
I_OH
Output logic high leakage V_O = 3.3 V
HIGH VOLTAGE TOLERANT LOGIC INPUT (WAKE)
VREG - 0.9
–1
0.5 V
V
1 μA
V_{IL_WAKE}
Output logic high voltage
V_{IH_WAKE}
Output logic high leakage
GATE DRIVE OUTPUT (GHx, GLx)
1.1
1.41 V
1.42
1.75 V
V_GHS
High side gate driver Vgs
voltage
V_GLS
Low-side gate driver Vgs
voltage
PEAK CURRENT DRIVE TIMES (GHx, GLx)
V_PVDD = 8 to 45 V; I_GATE < 30 mA
V_PVDD = 5.5 to 8 V; I_GATE < 10 mA
V_PVDD = 4.4 to 5.5 V; I_GATE < 5 mA
V_PVDD = 8 to 45 V; I_GATE < 30 mA
V_PVDD = 5.5 to 8 V; I_GATE < 10 mA
V_PVDD = 4.4 to 5.5 V; I_GATE < 5 mA
9
10
10.5
7
10.5 V
5
9
9
10
10.5
9
10.5 V
8
10.5
TDRIVEP = 00; TDRIVEN = 00
220
t_DRIVE
Peak sink or source current ^{TDRIVEP = 01; TDRIVEN = 01}
drive time
TDRIVEP = 10; TDRIVEN = 10
440
ns
880
TDRIVEP = 11; TDRIVEN = 11
1780
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