DRV8305-Q1_16 Datasheet, PDF (10/54 Pages) Texas Instruments – Three-Phase Automotive Gate Driver

DRV8305-Q1
SLVSD12A – MAY 2015 – REVISED MARCH 2016
www.ti.com
Electrical Characteristics (continued)
PVDD = 4.4 to 45 V, DRV8305xQ: T_J = –40°C to 150°C, DRV8305xE: T_J = –40°C to 175°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
CURRENT SHUNT AMPLIFIER
GAIN_CSx = 00
10
GAIN_CSx = 01
19.9
G_CSA
Current sense amplifier gain
GAIN_CSx = 10
39.8
GAIN_CSx = 11
79.5
G_ERR
t_SETTLING
V_IOS
V_{VREF_ERR}
V_DRIFTOS
I_BIAS
I_OFFSET
Current sense amplifier gain
error
Current sense amplifier
settling time
DC input offset
Reference buffer error (DC)
Input offset error drift
Input bias current
Input differential > 0.025 V;
T_J = –40 to 150 °C
Input differential > 0.025 V;
T_J = 150 to 175 °C
Settling time to 1%; no blanking;
G_CSA = 10; Vstep = 0.46 V
Settling time to 1%; no blanking;
G_CSA = 20; Vstep = 0.46 V
Settling time to 1%; no blanking;
G_CSA = 40; Vstep = 0.46 V
Settling time to 1%; no blanking;
G_CSA = 80; Vstep = 0.46 V
G_CSA = 10; input shorted; RTI
Internal or external VREF;
T_J = –40 to 150 °C
Internal or external VREF;
T_J = 150 to 175 °C
G_CSA = 10; input shorted; RTI
VIN_COM = 0; SOx open
Input bias current offset
IBIAS (SNx-SPx); VIN_COM = 0;
SOx open
–3%
3%
–4%
4%
300
600
1.2
2.4
–4
4
–2%
2%
–3%
3%
10
100
1
V_{IN_COM}
V_{IN_DIFF}
CMRR
Common input mode range
Differential input range
Common mode rejection
ration
External input resistance matched;
DC; GCSA = 10
External input resistance matched;
20 kHz; GCSA = 10
–0.15
-0.48
60
60
0.15
0.48
80
80
DC (<120 Hz); GCSA = 10
150
PSRR
Power supply rejection ratio
20 kHz; GCSA = 10
90
V_SWING
V_SLEW
I_VO
UGB
Output voltage swing
Output slew rate
Output short circuit current
Unity gain bandwidth
product
PVDD > 5.3 V
GCSA = 10; R_L = 0 Ω; CL = 60 pF
SOx shorted to ground
GCSA = 10
0.3
4.7
5.2
10
20
2
VOLTAGE PROTECTION
V_{AVDD_UVLO}
AVDD under voltage Fault
Relative to GND
VREG_UV_LEVEL = 00
3.3
3.5
VREG x 0.9
V_{VREG_UV}
VREG under voltage Fault
VREG_UV_LEVEL = 01
VREG_UV_LEVEL = 10
VREG x 0.8
VREG x 0.7
VREG_UV_LEVEL = 11
VREG x 0.7
V_{VREG_UV_DGL}
VREG under voltage
monitor deglitch time
1.5
2
V_{PVDD_UVFL}
Under voltage protection
warning, PVDD
PVDD falling
PVDD rising
7.7
8.1
7.9
8.3
UNIT
V/V
ns
µs
mV
µV/C
µA
µA
V
V
dB
dB
V
V/µs
mA
MHz
V
V
µs
V
10
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