DRV8305-Q1_16 Datasheet, PDF (20/54 Pages) Texas Instruments – Three-Phase Automotive Gate Driver

DRV8305-Q1
SLVSD12A – MAY 2015 – REVISED MARCH 2016
www.ti.com
7.3.3 VCPH Charge Pump: High-Side Gate Supply
The DRV8305-Q1 uses a charge pump to generate the proper gate to source voltage bias for the high-side N-
channel MOSFETs. Similar to the often used bootstrap architecture, the charge pump generates a floating supply
voltage used to enable the MOSFET. When enabled, the gate of the external MOSFET is connected to VCPH
through the internal gate drivers. The charge pump of the DRV8305-Q1 regulates the VCPH supply to PVDD +
10-V in order to support both standard and logic level MOSFETs. As opposed to a bootstrap architecture, the
charge pump supports 0 to 100% duty cycle operation by eliminating the need to refresh the bootstrap capacitor.
The charge pump also removes the need for bootstrap capacitors to be connected to the switch-node of the half-
bridge.
In order to support automotive cold crank transients on the battery which require the system to be operational to
as low as 4.4 V, a regulated triple charge pump scheme is used to create sufficient V_GS to drive standard and
logic level MOSFETs during the low voltage transient. Between 4.4 to 18 V the charge pump regulates the
voltage in a tripler mode. Beyond 18 V and until the max operating voltage, it switches over to a doubler mode in
order to improve efficiency. The charge pump is disabled until EN_GATE is set high to reduce unneeded power
consumption by the IC. After EN_GATE is set high, the device will go through a power up sequence to enable
the gate drivers and gate drive supplies. 1 ms should be allocated after EN_GATE is set high to allow the charge
pump to reach its regulation voltage.
The charge pump is continuously monitored for undervoltage and overvoltage conditions to prevent underdriven
or overdriven MOSFET scenarios. If an undervoltage or overvoltage condition is detected the appropriate actions
is taken and reported through the SPI registers.
7.3.4 VCP_LSD LDO: Low-Side Gate Supply
The DRV8305-Q1 uses a linear regulator to generate the proper gate to source voltage vias for the low-side N-
channel MOSFETs. The linear regulator generates a fixed 10-V supply voltage with respect to GND. When
enabled, the gate of the external MOSFET is connected to VCPH_LSD through the internal gate drivers. In order
to support automotive cold crank transients the input voltage for the VCP_LSD linear regulator is taken from the
VCPH charge pump. This allows the DRV8305-Q1 to provide sufficient V_GS to drive standard and logic level
MOSFETs during the low voltage transient.
The low-side regulator is disabled until EN_GATE is set high to reduce unneeded power consumption by the IC.
After EN_GATE is set high, the device will go through a power up sequence for the gate drivers and gate drive
supplies. 1 ms should be allocated after EN_GATE is set high to allow the low-side regulator to reach its
regulation voltage. The VCP_LSD regulator is continuously monitored for undervoltage conditions to prevent
underdriven MOSFET scenarios. If an undervoltage condition is detected the appropriate actions is taken and
reported through the SPI registers.
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