DRV8305-Q1_16 Datasheet, PDF (29/54 Pages) Texas Instruments – Three-Phase Automotive Gate Driver

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DRV8305-Q1
SLVSD12A – MAY 2015 – REVISED MARCH 2016
7.3.9 Undervoltage Warning (UVFL), Undervoltage Lockout (UVLO), and Overvoltage (OV) Protection
The DRV8305-Q1 implements undervoltage and overvoltage monitors on its system supplies to protect the
system, prevent brownout conditons, and prevent unexpected device behavior. Undervoltage is monitored for on
the PVDD, AVDD, VREF, VCPH, and VCP_LSD power supplies. Overvoltage is monitored for on the PVDD and
VCPH power supplies. The values for the various undervoltage and overvoltage levels are provided in the
electrical characteristics table under the voltage protection section.
The monitors for the main power supply, PVDD, incorporates several additional features:
• Undervoltage warning (PVDD_UVFL) level. Device operation is not impacted, report only indication.
• PVDD_UVFL is warning type error indicated on the nFAULT pin and the PVDD_UVFL status bit in register
0x1, bit D7
• Independent UVLO levels for the gate driver (PVDD_UVLO2) and VREG LDO regulator (PVDD_UVLO1).
PVDD_UVLO2 will trigger a shutdown of the gate driver
• PVDD_UVLO2 is a fault type error indicated on the nFAULT pin and corresponding status bit in register 0x3,
bit D10
• PVDD_UVLO2 may be disabled through the DIS_VPVDD_UVLO setting in register 0x9, bit D9. The fault will
still be reported in the status bit in register 0x3, bit D10
• Overvoltage detection to monitor for load dump or supply pumping conditions. Device operation is not
impacted, report only indication
• PVDD_OV is a warning type error indicated on the nFAULT pin and the PVDD_OV bit in register 0x1, bit D6
The monitors for the high-side charge pump supply, VCPH, and low-side supply (VCP_LSD) incorporate several
additional features:
• VCPH relative (VCPH_OVLO) and absolute overvoltage (VCPH_OVLO_ABS) detection. The DRV8305-Q1
monitors VCPH for overvoltage conditions with respect to PVDD and GND
• VCPH_OVLO and VCPH_OVLO_ABS are fault type errors reported on nFAULT and the corresponding status
bit in register 0x3, bits D1-D0
• VCPH undervoltage (VCPH_UVLO2) is monitored to prevent underdriven MOSFET conditions.
VCPH_UVLO2 will trigger a shutdown of the gate driver
• VCPH_UVLO2 is a fault type error indicated on the nFAULT pin and corresponding status bit in register 0x3,
bit D2
• VCP_LSD undervoltage (VCP_LSD_UVLO2) is monitored to prevent underdriven MOSFET conditions.
VCP_LSD_UVLO2 will trigger a shutdown of the gate driver
• VCP_LSD_UVLO2 is a fault type error indicated on the nFAULT pin and corresponding status bit in register
0x3, bit D4
• Undervoltage proteciton for VCPH and VCP_LSD may not be disabled in the operating state
7.3.9.1 Overtemperature Warning (OTW) and Shutdown (OTSD) Protection
A multi-level temperature detection circuit is implemented in the DRV8305-Q1.
• Flag Level 1 (TEMP_FLAG1): Level 1 overtemperature flag. No warning reported on nFAULT. Real-time flag
indicated in SPI register 0x1, bit D3.
• Flag Level 2 (TEMP_FLAG2): Level 2 overtemperature flag. No warning reported on nFAULT. Real-time flag
indicated in SPI register 0x1, bit D2.
• Flag Level 3 (TEMP_FLAG3): Level 3 overtemperature flag. No warning reported on nFAULT. Real-time flag
indicated in SPI register 0x1, bit D1.
• Flag Level 4 (TEMP_FLAG4): Level 4 overtemperature flag. No warning reported on nFAULT. Real-time flag
indicated in SPI register 0x1, bit D8.
• Warning Level (OTW): Overtemperature warning only. Warning reported on nFAULT. Real-time flag indicated
in SPI register 0x1, bit D0.
• Fault Level (OTSD): Overtemperature fault and latched shut down of the device. Fault reported on nFAULT
and in SPI register 0x3, bit D8.
SPI operation is still available and register settings will be retained in the device during OTSD operation as long
as PVDD is within operation range. An OTSD fault can be cleared when the device temperature has dropped
below the fault level and a CLR_FLTS is issued.
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