DRV8305-Q1_16 Datasheet, PDF (49/54 Pages) Texas Instruments – Three-Phase Automotive Gate Driver

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10 Layout
DRV8305-Q1
SLVSD12A – MAY 2015 – REVISED MARCH 2016
10.1 Layout Guidelines
Use the following layout recommendations when designing a PCB for the DRV8305-Q1.
• The DVDD and AVDD 1-μF bypass capacitors should connect directly to the adjacent GND pin to minimize
loop impedance for the bypass capacitor.
• The CP1 and CP2 0.047-μF flying capacitors should be placed directly next to the DRV8305-Q1 charge pump
pins.
• The VCPH 2.2-μF and VCP_LSD 1-μF bypass capacitors should be placed close to their corresponding pins
with a direct path back to the DRV8305-Q1 GND net.
• The PVDD 4.7-μF bypass capacitor should be placed as close as possible to the DRV8305-Q1 PVDD supply
pin.
• Use the proper footprint as shown in the mechanical drawing.
• Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the DRV8305-
Q1 GH_X to the power MOSFET and returns through SH_X. The low-side loop is from the DRV8305-Q1
GL_X to the power MOSFET and returns through SL_X.
• The VDRAIN pin is used to sense the DRAIN voltage of the high-side MOSFETs for the V_DS overcurrent
monitors. It should route through the 100 Ω series resistor directly to the MOSFET DRAIN, ideally at the
midpoint of the half-bridge connections in order to get the most accurate sense point.
10.2 Layout Example
PVDD
4.7 µF
VCC
1 µF
PVDD
100
1 µF
0.047 µF
2.2 µF
0.047 µF
1 µF
D
G
D
S
D
S
OUTA
D
S
VCC
10 k
1 EN_GATE
2 INHA
3 INLA
4 INHB
5 INLB
6 INHC
7 INLC
8 nFAULT
9 nSCS
10 SDI
11 SDO
12 SCLK
PWR_PAD (0) - GND
DRV8305
GH_A 36
SH_A 35
SL_A 34
GL_A 33
GL_B 32
SL_B 31
SH_B 30
GH_B 29
GH_C 28
SH_C 27
SL_C 26
GL_C 25
5m
S
S
S
G
D
D
D
D
5m
S
S
S
G
D
D
D
D
G
S
S
OUTB
S
D
D
D
D
VCC
10 k
1 µF
Legend
Top Layer
Via
D
D
D
D
5m
S
S
S
G
G
S
S
OUTC
S
D
D
D
D
Figure 24. Layout Recommendation
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