DRV8305-Q1_16 Datasheet, PDF (24/54 Pages) Texas Instruments – Three-Phase Automotive Gate Driver

DRV8305-Q1
SLVSD12A – MAY 2015 – REVISED MARCH 2016
www.ti.com
not include delay from internal amplifier loading or delays from the trace or component loads on the amplifier
output. The programmable blanking time may be overridden to have no delay (default value).
• Minimize DC offset and drift through temperature with DC calibrating through SPI register. When DC
calibration is enabled, device will short input of current shunt amplifier and disconnect the load. DC calibrating
can be done at anytime, even when the MOSFET is switching because the load is disconnected. For best
result, perform the DC calibrating during switching off period when no load is present to reduce the potential
noise impact to the amplifier.
The output of current shunt amplifier can be calculated as:
V_O
V_VREF
k
G u SN_X
SP_X
where
• VREF is the reference voltage from the VREG pin.
• G is the gain setting of the amplifier.
• k = 2 or 4
• SNx and SPx are the inputs of channel x.
• SPx should connect to the low-side (ground) of the sense resistor for the best common mode rejection.
• SNx should connect to the high-side (LS MOSFET source) of the sense resistor.
(1)
Figure 12 shows current amplifier simplified block diagram.
400 k
S4
DC _ CAL(SPI)
200 k
S3
100 k
S2
50 k
S1
SN
5k
_
AVDD
100
S5
SO
5k
+
SP
DC _ CAL(SPI)
50 k
S1
100 k
S2
200 k
S3
400 k
S4
VREF
_
AVDD
VREF/k
k = 2, 4
+
Figure 12. Current Shunt Amplifier Simplified Block Diagram
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