DRV8305-Q1_16 Datasheet, PDF (26/54 Pages) Texas Instruments – Three-Phase Automotive Gate Driver

DRV8305-Q1
SLVSD12A – MAY 2015 – REVISED MARCH 2016
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The second error class is a Fault. Fault errors will trigger a shutdown of the gate driver with its major blocks and
are reported by holding nFAULT low with the corresponding status register asserted. Fault errors are latched
until the appropriate recovery sequence is performed.
• A fault error is reported by holding the nFAULT pin low and asserting the FAULT bit in register 0x1
• The error type will also be asserted in the SPI registers
• A fault error is a latched fault and must be cleared with the appropriate recovery sequence
• If a fault occurs during a warning error, the fault error will take precendence, latch nFAULT low and shutdown
the gate driver
• The output MOSFETs will be placed into their high impedance state in a fault error event
• To recover from a fault type error, the condition must be removed and the CLR_FLTs bit asserted in register
0x9, bit D1 or an EN_GATE reset pulse issued
• The CLR_FLTS bit self clears to 0 after fault status reset and nFAULT pin is released
There are two exceptions to the fault and warning error classes. The first exception is the temperature flag
warnings (TEMP_FLAGX). A Temperature Flag warning will not trigger any action on the nFAULT pin and the
corresponding status bit will be updated in real time. See the overtemperature section for additional information.
The second exception is the MCU Watchdog and VREG Undervoltage (VREG_UV) faults. These are reported on
the PWRGD pin to protect the system from lock out and brownout conditions. See their corresponding sections
for additional information.
Note that nFAULT is an open-drain signal and must be pulled up through an external resistor.
7.3.8.2 MOSFET Shoot-Through Protection (TDRIVE)
DRV8305-Q1 integrates analog handshaking and digital dead time to prevent shoot-through in the external
MOSFETs.
• An internal handshake through analog comparators is performed between each high-side and low-side
MOSFET switching transaction (see TDRIVE: Gate Driver State Machine). The handshake monitors the
voltage between the gate and source of the external MOSFET to ensure the device has reached its cutoff
threshold before enabling the opposite MOSFET.
• A minimum dead time (digital) of 40 ns is always inserted after each successful handshake. This digital dead
time is programmable through the DEAD_TIME SPI setting in register 0x7, bits D6-D4 and is in addition to the
time taken for the analog handshake.
7.3.8.3 MOSFET Overcurrent Protection (VDS_OCP)
To protect the system and external MOSFET from damage due to high current events, V_DS overcurrent monitors
are implemented in the DRV8305-Q1.
The V_DS sensing is implemented for both the high-side and low-side MOSFETs through the pins below:
• High-side MOSFET: V_DS measured between VDRAIN and SHx pins
• Low-side MOSFET: V_DS measured between SHx and SLx pins
Based on the R_DS(on) of the power MOSFETs and the maximum allowed I_DS, a voltage threshold can be
calculated, which when exceeded, triggers the V_DS overcurrent protection feature. The voltage threshold level
(VDS_LEVEL) is programmable through the SPI VDS_LEVEL setting in register 0xC, bits D7-D3 and may be
changed during gate driver operation if needed.
The V_DS overcurrent monitors implement adjustable blanking and deglitch times to prevent false trips due to
switching voltage transients. The V_DS blanking time (t_BLANK) is inserted digitally and programmable through the
SPI TBLANK setting in register 0x7, bits D3-D2. The t_BLANK time is inserted after each switch ON transistion
(LOW to HIGH) of the output gate drivers is commanded. During the t_BLANK time, the V_DS comparators are not
being monitored in order to prevent false trips when the MOSFET first turns ON. After the t_BLANK time expires the
overcurrent monitors will begin actively watching for an overcurrent event.
The V_DS deglitch time (t_VDS) is inserted digitally and programmable through the SPI TVDS setting in register 0x7,
bits D1-D0. The t_VDS time is a delay inserted after the V_DS sensing comparators have tripped to when the
protection logic is informed that a V_DS event has occurred. If the overcurrent event does not persist through t_VDS
delay then it will be ignored by the DRV8305-Q1.
Note that the dead time and blanking time are overlapping timers as shown in Figure 13.
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