DRV8305-Q1_16 Datasheet, PDF (13/54 Pages) Texas Instruments – Three-Phase Automotive Gate Driver

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6.6 SPI Timing Requirements (Slave Mode Only)
t_{SPI_READY}
t_CLK
t_CLKH
t_CLKL
t_{SU_SDI}
t_{HD_SDI}
t_{D_SDO}
t_{HD_SDO}
t_{SU_SCS}
t_{HD_SCS}
t_{HI_SCS}
tACC
t_DIS
SPI read after power on
Minimum SPI clock period
PVDD > V_{PVDD_UVLO1}
Clock high time
Clock low time
SDI input data setup time
SDI input data hold time
SDO output data delay time, CLK high to SDO valid C_L = 20 pF
SDO output hold time
SCS setup time
SCS hold time
SCS minimum high time before SCS active low
SCS access time, SCS low to SDO out of high impedance
SCS disable time, SCS high to SDO high impedance
SCS
t_{HI_SCS}
t_{SU_SCS}
DRV8305-Q1
SLVSD12A – MAY 2015 – REVISED MARCH 2016
MIN
NOM
5
100
40
40
20
30
40
50
50
400
10
10
t_{HD_SCS}
MAX
10
20
UNIT
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK
SDI
t_CLK
t_CLKH
t_CLKL
t_{SU_SDI}
MSB In
(Must Be Valid)
t_{HD_SDI}
LSB
SDO
Z
t_ACC
MSB Out (Is Valid)
LSB
t_{D_SDO}
t_{HD_SDO}
Figure 1. SPI Slave Mode Timing Definition
Z
t_DIS
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