DRV8305-Q1_16 Datasheet, PDF (11/54 Pages) Texas Instruments – Three-Phase Automotive Gate Driver

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DRV8305-Q1
SLVSD12A – MAY 2015 – REVISED MARCH 2016
Electrical Characteristics (continued)
PVDD = 4.4 to 45 V, DRV8305xQ: T_J = –40°C to 150°C, DRV8305xE: T_J = –40°C to 175°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
V_{PVDD_UVLO1}
Under voltage protection
lock out, PVDD
PVDD falling
PVDD rising
4.1
4.3
V_{PVDD_UVLO2}
Under voltage protection
fault, PVDD
PVDD falling
PVDD rising
4.2
4.4
4.4
4.6
V_{PVDD_OVFL}
Overvoltage protection
warning, PVDD
PVDD falling
PVDD rising
33.5
36
32.5
35
V_{VCPH_UVFL}
Charge pump under voltage
protection warning, VCPH
Relative to PVDD
8
V_{VCPH_UVLO2}
Charge pump under voltage ^{Relative to PVDD, SET_VCPH_UV = 0}
protection fault, VCPH
Relative to PVDD, SET_VCPH_UV = 1
4.5
4.2
4.9
4.6
V_{VCP_LSD_UVLO2}
Low-side regulator under
voltage fault, VCP_LSD
Relative to GND
6.4
7.5
V_{VCPH_OVLO}
Charge pump over voltage
protection fault, VCPH
Relative to PVDD
14
18
V_{VCPH_OVLO_ABS}
Charge pump over voltage
protection fault, VCPH
Relative to GND
60
TEMPERATURE PROTECTION
OTW_CLR
Junction temperature to
clear over temperature
(OTW) warning⁽¹⁾
100
130
150
OTW_SET
Junction temperature for
over temperature (OTW)
warning ⁽¹⁾
135
160
185
OTSD_CLR
Junction temperature to
clear over temperature
shutdown (OTSD)⁽¹⁾
125
155
180
OTSD_SET ⁽²⁾
Junction temperature for
over temperature shutdown
(OTSD) ⁽¹⁾
160
185
210
TEMP_FLAG1
Junction temperature flag
setting 1⁽¹⁾
105
TEMP_FLAG2
Junction temperature flag
setting 2⁽¹⁾
125
TEMP_FLAG3
Junction temperature flag
setting 3⁽¹⁾
135
TEMP_FLAG4
Junction temperature flag
setting 4⁽¹⁾
185
PROTECTION CONTROL
t_pd,E-L
Delay, error event to all
gates low
TBLANK = 00; TVDS = 00
1
t_pd,E-SD
Delay, error event to
nFAULTx low
TBLANK = 00; TVDS = 00
1
UNIT
V
V
V
V
V
V
V
V
°C
°C
°C
°C
°C
°C
°C
°C
µs
µs
(1) Specified by design
(2) Overtemperature shutdown (OTSD) is disabled by default for DRV8305xEPHPQ1 and may only be re-enabled through control register.
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