DRV8305-Q1_16 Datasheet, PDF (25/54 Pages) Texas Instruments – Three-Phase Automotive Gate Driver

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DRV8305-Q1
SLVSD12A – MAY 2015 – REVISED MARCH 2016
7.3.6 DVDD and AVDD: Internal Voltage Regulators
The DRV8305-Q1 has two internal regulators, DVDD and AVDD, that power internal circuitry. These regulators
cannot be used to drive external loads and may not be supplied externally.
DVDD is the voltage regulator for the internal logic circuits and is maintained at a value of 3.3 V through the
entire operating range of the device. DVDD is derived from the PVDD power supply. DVDD should be bypassed
externally with a 1-µF capacitor to GND.
AVDD is the voltage regulator that provides the voltage rail for the internal analog circuit blocks including the
current sense amplifiers and is maintained at a value 5.0 V. AVDD is derived from the PVDD voltage power
supply. AVDD should be bypassed externally with a 1-µF capacitor to GND.
Because the allowed PVDD operating range of the device permits operation below the nominal value of AVDD,
this regulator operates in two regimes: namely a linear regulating regime and a dropout region. In the dropout
region, the AVDD will simply track the PVDD voltage minus a voltage drop.
If the device is expected to operate within the dropout region, take care while selecting current sense amplifier
components and settings to accommodate the reduced voltage rail.
7.3.7 VREG: Voltage Regulator Output
The DRV8305-Q1 integrates a 50 mA, LDO voltage regulator (VREG) that is dedicated for driving external loads
such as an MCU directly. The VREG regulator also supplies the reference for the SDO output of the SPI bus and
the voltage reference for the amplifier output bias. The three different DRV8305-Q1 device versions provide
different configurations for the VREG output. For the DRV83053Q, the VREG output is regulated at 3.3 V. For
the DRV83055Q, the VREG output is regulated at 5.0 V. For the DRV8305NQ and DRV8305NE, the VREG
voltage regulator is disabled (VREG pin used for reference voltage) and the reference voltage for SDO and the
amplifier output bias must be supplied from an external supply to the VREG pin.
The DRV8305-Q1 VREG voltage regulator also features a PWRGD pin to protect against brownouts on
externally driven devices. The PWRGD pin is often tied to the reset pin of a microcontroller to ensure that the
microcontroller is always reset when the VREG output voltage is outside of its recommended operation area.
When the voltage output of the VREG regulator drops or exceeds the set threshold (programmable).
• The PWRGD pin will go low for a period of 56 µs.
• After the 56 µs period has expired, the VREG voltage will be checked and PWRGD will be held low until the
VREG voltage has recovered.
The voltage regulator also has undervoltage protection implemented for both the input voltage (PVDD) and
output voltage (VREG).
7.3.8 Protection Features
7.3.8.1 Fault and Warning Classification
The DRV8305-Q1 integrates extensive error detection and monitoring features. These features allow the design
of a robust system that can protect against a variety of system related failure modes. The DRV8305-Q1 classifies
error events into two categories and takes different device actions dependent on the error classification.
The first error class is a Warning. There are several types of conditions that are classified as warning only.
Warning errors are report only and the DRV8305-Q1 will take no other action effecting the gate drivers or other
blocks. When a warning condition occurs it will be reported in the corresponding SPI status register bit and on
the nFAULT pin with a repeating 56 µs pulse low followed by a 56 µs pulse high. A warning error can be cleared
by an SPI read to the corresponding status register bit. The same warning will not be reported through the
nFAULT pin again unless that warning or condition passes and then reoccurs.
• A warning error is reported on the nFAULT pin with a repeating 56 µs pulse low followed by a 56 µs pulse
high
• The warning is reported on the nFAULT pin until a SPI read to the corresponding status register
• The SPI read will clear the nFAULT report, but the SPI register will remain asserted until the condition has
passed
• The nFAULT pin will report a new warning if the condition clears and then occurs again
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