DRV8305-Q1_16 Datasheet, PDF (33/54 Pages) Texas Instruments – Three-Phase Automotive Gate Driver

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DRV8305-Q1
SLVSD12A – MAY 2015 – REVISED MARCH 2016
Device Functional Modes (continued)
7.4.5 Limp Home or Fail Code Operation
The DRV8305-Q1 enables the adoption of secondary limp-home or fail code software through configurable fault
mode handling. The following device features may be configured during the operating state without stopping the
motor.
• IDRIVE Gate Current Output (IDRIVEN_HS, IDRIVEP_HS, IDRIVEN_LS, IDRIVEP_LS): All four IDRIVEX
settings may be adjusted during normal operation without issue. This features allows the software to change
the slew rate, switching characteristics of the external MOSFETs on the fly if required without having to stop
the motor rotation. The IDRIVEX settings are located in the SPI registers 0x5 (high-side) and 0x6 (low-side)
• VDS Fault Mode (VDS_MODE): The V_DS overcurrent monitors may be changed from latched shut down
(VDS_MODE = b'000) or report only (VDS_MODE = b'001) modes to disabled (VDS_MODE = b'010) mode to
allow operation of the external MOSFETs past normal operating conditions. This is the only VDS_MODE
change allowed in the operating state. The VDS_MODE setting is located in the SPI register 0xC, bits D2-D0.
• VDS Comparator Thresholds (VDS_LEVEL): The V_DS overcurrent monitor threshold (VDS_LEVEL) may be
changed at any time during operation to allow for higher that standard operating currents. The VDS_LEVEL
setting is located in the SPI register 0xC.
• VGS Fault Mode (DIS_GDRV_FAULT): The V_GS fault detection monitors can be disabled through the SPI
register 0x9, bit D8. Reporting in SPI will also be disabled as a result.
• SNS_OCP Fault Mode (DIS_SNS_OCP): The sense amplifer overcurrent monitors can be disabled through
the SPI register 0x9, bit D4. Reporting in SPI will also be disabled as a result.
• PVDD Underoltage Lockout (DIS_VPVDD_UVLO2): The main power supply undervoltage lockout can be
disabled through the SPI register 0x9, but D9. Reporting in SPI will also be disabled as a result.
• OTSD Overtemperature Shutdown (FLIP_OTS): The overtemperature shutdown can be disabled through the
SPI register 0x9, bit D10. Reporting in SPI will also be disabled as a result. The OTS overtemperature
shutdown is disabled by default on the Grade 0, DRV8305xE device.
Unpowered System
PVDD < VPVDD_UVLO1
Sleep
PVDD > VPVDD_UVLO2
PVDD < VPVDD_UVLO1
NO
WAKE >
WAKE_VIH
WAKE > WAKE_VIH
YES
Sleep = 1 through SPI
Operating
EN_GATE = High
EN_GATE = Low
Figure 16. Operating States
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Product Folder Links: DRV8305-Q1
Standby
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