DRV8305-Q1_16 Datasheet, PDF (41/54 Pages) Texas Instruments – Three-Phase Automotive Gate Driver

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DRV8305-Q1
SLVSD12A – MAY 2015 – REVISED MARCH 2016
7.6.2.4 IC Operation (Address = 0x9)
Table 17. IC Operation Register Description
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10
R/W
FLIP_OTSD
0x0
Enable OTSD⁽¹⁾
b'0 - Disable OTSD
b'1 - Enable OTSD
9
R/W
DIS_PVDD_UVLO2 0x0
Disable PVDD_UVLO2 fault and reporting
b'0 - PVDD_UVLO2 enabled
b'1 - PVDD_UVLO2 disabled
8
R/W
DIS_GDRV_FAULT 0x0
Disable gate drive fault and reporting
b'0 - Gate driver fault enabled
b'1 - Gate driver fault disabled
7
R/W
EN_SNS_CLAMP
0x0
Enable sense amplifier clamp
b'0 - Sense amplifier clamp is not enabled
b'1 - Sense amplifier clamp is enabled, limiting output to ~3.3 V
6:5
R/W
WD_DLY
0x1
Watchdog delay
b'00 - 10 ms
b'01 - 20 ms
b'10 - 50 ms
b'11 - 100 ms
4
R/W
DIS_SNS_OCP
0x0
Disable SNS overcurrent protection fault and reporting
b'0 - SNS OCP enabled
b'1 - SNS OCP disabled
3
R/W
WD_EN
0x0
Watchdog enable
b'0 - Watch dog disabled
b'1 - Watch dog enabled
2
R/W
SLEEP
0x0
Put device into sleep mode
b'0 - Device awake
b'1 - Device asleep
1
R/W
CLR_FLTS
0x0
Clear faults
b'0 - Normal operation
b'1 - Clear faults
0
R/W
SET_VCPH_UV
0x0
Set charge pump undervoltage threshold level
b'0 - 4.9 V
b'1 - 4.6 V
(1) Overtemperature shutdown (OTSD) is disabled by default for DRV8305xEPHPQ1 and may only be re-enabled through this control bit.
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