DRV8305-Q1_16 Datasheet, PDF (32/54 Pages) Texas Instruments – Three-Phase Automotive Gate Driver

DRV8305-Q1
SLVSD12A – MAY 2015 – REVISED MARCH 2016
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7.4 Device Functional Modes
7.4.1 Power Up Sequence
The DRV8305-Q1 has an internal state machine to ensure proper power up and power down sequencing of the
device. When PVDD power is applied the device will remain inactive until PVDD cross the digital logic threshold.
At this point, the digital logic will become active, VREG will enable (if 3.3V or 5V device option is used), the
passive gate pull downs will enable, and nFAULT will be driven low to indicate that the device has not reached
the V_{PVDD_UVLO2} threshold. nFAULT will remain driven low until PVDD crosses the PVDD_UVLO threshold. At this
point the device will enter its standby state.
PVDD
nFAULT
(Active Low)
X
PVDD_UVLO2
Logic
Threshold
Power Up
Complete
Logic Reset
Figure 15. Power-Up Sequence
7.4.2 Standby State
After the power up sequence is completed and the PVDD voltage is above V_{PVDD_UVLO2} threshold, the DRV8305-
Q1 will indicate successful and fault free power up of all circuits by releasing the nFAULT pin. At this point the
DRV8305-Q1 will enter its standby state and be ready to accept inputs from the external controller. The
DRV8305-Q1 will remain in or re-enter its standby state anytime EN_GATE = LOW or a fault type error has
occured. In this state the major gate driver blocks are disabled, but the passive gate pulldowns are still active to
maintain the external MOSFETs in their high impedence state. It is recommended, but not required to perform all
device configurations through SPI in the standby state.
7.4.3 Operating State
After reaching the standby state and then taking EN_GATE from LOW to HIGH, the DRV8305-Q1 will enter its
operating state. The operating state enables the major gate driver and current shunt amplifier blocks for normal
operation. 1 ms should be allowed after EN_GATE is taken HIGH to allow the charge pump supply for the high-
side gate drivers to reach its steady state operating point. If at any point in its operating state a fault type error
occurs, the DRV8305-Q1 will immedietely re-enter the standby state.
7.4.4 Sleep State
The sleep state can be entered by issuing a sleep command through the SLEEP bit in SPI register 0x9, bit D2
with the device in its standby state (EN_GATE = LOW). The device will not respond to a sleep command in its
operating state. After the sleep command is received, the gate drivers and output regulator (VREG) will safely
power down after a programmable delay set in the SPI register 0xB, bits D4-D3. The device can then only be
enabled through the WAKE pin which is a high-voltage tolerant input pin. For the DRV8305-Q1 to be brough out
of sleep, the WAKE pin must be at a voltage greater than 3 V. This allows the wake pin to be driven, for
example, directly by the battery through a switch, through the inhibit pin (INH) on a standard LIN interface, or
through standard digital logic. The WAKE pin will only react to a wake up command if PVDD > V_{PVDD_UVLO2}. After
the DRV8305-Q1 is out of SLEEP mode, all activity on the WAKE pin is ignored. The sleep state erases all
values in the SPI control registers and it is not recommended to write through SPI in the sleep state.
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