DS90UR903Q-Q1 Datasheet, PDF (5/44 Pages) Texas Instruments – 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer

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DS90UR903Q-Q1, DS90UR904Q-Q1
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
DS90UR904Q Deserializer Pin Descriptions
PIN
NAME
NUMBER
I/O, TYPE
DESCRIPTION
LVCMOS PARALLEL INTERFACE
ROUT[20:0]
5, 6, 8, 9, 10,
11, 12, 13, 14,
15, 16, 18, 19,
21, 22, 23, 24,
25, 26, 27, 28
Outputs,
LVCMOS
Parallel data outputs.
PCLK
4
Output,
LVCMOS
SERIAL CONTROL BUS - I²C COMPATIBLE
Pixel Clock Output Pin.
Strobe edge set by RRFB control register.
SCL
SDA
MODE
2
Input,
Clock line for the serial control bus communication
Open Drain SCL requires an external pull-up resistor to V_DDIO.
1
Input/Output, Data line for the serial control bus communication
Open Drain SDA requires an external pull-up resistor to V_DDIO.
47
Input, LVCMOS
w/ pull up
I²C Mode select
MODE = H -REQUIRED. The MODE pin must be set HIGH to allow I²C configuration
of the deserializer.
ID[x]
9
Input, analog
Device ID Address Select
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 2
CONTROL AND CONFIGURATION
PDB
Power down Mode Input Pin.
35
Input, LVCMOS
w/ pull down
PDB = H, Deserializer is enabled and is ON.
PDB = L, Deserializer is in Power Down mode. When the Deserializer is in Power
Down. Programmed control register data are NOT retained and reset to default
values.
LOCK
LOCK Status Output Pin.
34
Output,
LVCMOS
LOCK = H, PLL is Locked, outputs are active
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL control register. May be used as Link Status.
RES
37, 38, 39, 43,
44, 46
Reserved.
-
Pin 46: This pin MUST be tied LOW.
Pin 37, 43, 44: Leave pin open.
Pins 38, 39: Route to test point or leave open if unused.
NC
30, 31, 32, 33
No Connect
FPD-LINK II INTERFACE
RIN+
41
Input, CML
Noninverting differential input. The interconnect must be AC Coupled with a 100 nF
capacitor.
RIN-
42
POWER AND GROUND ⁽¹⁾
Inputt, CML
Inverting differential input. The interconnect must be AC Coupled with a 100 nF
capacitor.
VDDSSCG
3
Power, Digital
SSCG Power, 1.8V ±5%
Power supply must be connected regardless if SSCG function is in operation.
VDDIO1/2/3
VDDD
29, 20, 7
17
Power, Digital
Power, Digital
LVCMOS I/O Buffer Power, The single-ended outputs and control input are powered
from V_DDIO. V_DDIO can be connected to a 1.8V ±5% or 3.3V ±10%
Digital Core Power, 1.8V ±5%
VDDR
36
Power, Analog Rx Analog Power, 1.8V ±5%
VDDCML
40
Power, Analog 1.8V ±5%
VDDPLL
45
Power, Analog PLL Power, 1.8V ±5%
VSS
DAP
DAP must be grounded. DAP is the large metal contact at the bottom side, located at
Ground, DAP the center of the WQFN package. Connected to the ground plane (GND) with at least
16 vias.
(1) See Power Up Requirements and PDB PIN.
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