DS90UR903Q-Q1 Datasheet, PDF (30/44 Pages) Texas Instruments – 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer

DS90UR903Q-Q1, DS90UR904Q-Q1
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
www.ti.com
70
1960
60
1680
50
1400
40
1120
30
840
DS90UR903Q/904Q
20
560
10
280
0
0
0
5
10
15
20
25
CABLE LENGTH (m)
*Note: Equalization is enabled for cable lengths greater than 7 meters
Figure 32. Rosenberger HSD & Leoni DACAR 538 Cable Performance
8.2.2.5 Serial Interconnect Guidelines
For full details, see the Channel-Link PCB and Interconnect Design-In Guidelines (literature number SNLA008)
and the Transmission Line RAPIDESIGNER Operation and Applications Guide (literature number SNLA035).
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
Additional general guidance can be found in the LVDS Owner’s Manual (literature number SNLA187), which is
available in PDF format from the TI LVDS & CML Solutions web site.
8.2.2.6 Application Curves
Time (200 ps/DIV)
Figure 33. Serializer Eye Diagram at 1.2 Gbps Line Rate
(43MHz Pixel Clock)
Time (4 ns/DIV)
Figure 34. Serializer CML Output with 43MHz TX Pixel
Clock
30
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