DS90UR903Q-Q1 Datasheet, PDF (19/44 Pages) Texas Instruments – 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer

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Graphics
Controller
---
Video
Processor
2C
DS90UR903Q-Q1, DS90UR904Q-Q1
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
DS90UR903Q
Serializer
DS90UR904Q
Deserializer
FPD-Link II
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
PCLK
Timing
Controller
PCLK
PDB
MODE
SDA
SCL
PLL
Config.
Config.
PDB
MODE
LCD
Display
SDA
SCL
2C
Figure 22. Application Block Diagram
7.3 Feature Description
7.3.1 Serial Frame Format
The DS90UR903Q/904Q chipset will transmit and receive a pixel of data in the following format:
Bit 0 to Bit 20
Figure 23. Serial Bitstream for 28-bit Symbol
The High Speed Serial Channel is a 28-bit symbol composed of 21 bits of data containing video data & control
information transmitted from Serializer to Deserializer. CLK1 and CLK0 represent the embedded clock in the
serial stream. CLK1 is always HIGH and CLK0 is always LOW. This data payload is optimized for signal
transmission over an AC coupled link. Data is randomized, balanced and scrambled.
7.3.2 Signal Quality Enhancers
7.3.2.1 Des - Receiver Input Equalization (EQ)
The receiver inputs provided input equalization filter in order to compensate for loss from the media. The level of
equalization is controlled via register setting.
7.3.3 Emi Reduction
7.3.3.1 Des - Receiver Staggered Output
The Receiver staggered outputs allows for outputs to switch in a random distribution of transitions within a
defined window. Outputs transitions are distributed randomly. This minimizes the number of outputs switching
simultaneously and helps to reduce supply noise. In addition it spreads the noise spectrum out reducing overall
EMI.
7.3.3.2 Des Spread Spectrum Clocking
The DS90UR904Q parallel data and clock outputs have programmable SSCG ranges from 9 kHz–66 kHz and
±0.5%–±2% from 20 MHz to 43 MHz. The modulation rate and modulation frequency variation of output spread is
controlled through the SSC control registers.
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