DS90UR903Q-Q1 Datasheet, PDF (22/44 Pages) Texas Instruments – 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer

DS90UR903Q-Q1, DS90UR904Q-Q1
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
www.ti.com
7.6 Register Maps
ADDR
(HEX)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
NAME
I²C Device ID
Reset
Reserved
Reserved
VDDIO Control
VDDIO Mode
RESERVED
RESERVED
PCLK_AUTO
TRFB
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCLK Detect
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 3. DS90UR903Q Control Registers
BITS
FIELD
7:1 DEVICE ID
0 SER ID SEL
7:3 RESERVED
2 RESERVED
1
DIGITAL
RESET0
0 DIGITAL RESET1
7:0 RESERVED
7:6 RESERVED
5 VDDIO CONTOL
4 VDDIO MODE
3 RESERVED
2 RESERVED
1 PCLK_AUTO
0 TRFB
7:0 RESERVED
7:0 RESERVED
7:0 RESERVED
7:0 RESERVED
7:0 RESERVED
7:0 RESERVED
7:0 RESERVED
7:0 RESERVED
7:3 RESERVED
2 PCLK DETECT
3 RESERVED
0 RESERVED
7:0 RESERVED
7:0 RESERVED
7:0 RESERVED
7:0 RESERVED
7:0 RESERVED
7:0 RESERVED
R/W DEFAULT
DESCRIPTION
7-bit address of Serializer; 0x58'h
(1011_000X'b) default
RW
0xB0'h
0: Device ID is from ID[x]
1: Register I²C Device ID overrides ID[x]
0x00'h Reserved
RW
0
Reserved
RW
0
1: Resets the device to default register values. Does not
self clear affect device I²C Bus or Device ID
RW
0
1: Digital Reset, retains all register values
self clear
0x20'h Reserved
11'b Reserved
Auto VDDIO detect
RW
1
Allows manual setting of VDDIO by register.
0: Disable
1: Enable (auto detect mode)
VDDIO voltage set
RW
1
Only used when VDDIOCONTROL = 0
0: 1.8V
1: 3.3V
RW
1
Reserved
0
Reserved
Switch over to internal 25 MHz Oscillator clock in the
RW
1
absence of PCLK
0: Disable
1: Enable
Pixel Clock Edge Select:
0: Parallel Interface Data is strobed on the Falling Clock
RW
1
TRFB 0 TRFB RW 1 Edge.
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
0x80'h Reserved
RW
0x40'h Reserved
RW
0xC0'h Reserved
RW
0x00'h Reserved
0x00'h Reserved
0x01'h Reserved
0x00'h Reserved
0x00'h Reserved
0x00'h Reserved
R
0
1: Valid PCLK detected
0: Valid PCLK not detected
0
Reserved
R
0
Reserved
0x11'h Reserved
0x01'h Reserved
0x03'h Reserved
0x03'h Reserved
0x03'h Reserved
0x03'h Reserved
22
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