DS90UR903Q-Q1 Datasheet, PDF (16/44 Pages) Texas Instruments – 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer

DS90UR903Q-Q1, DS90UR904Q-Q1
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
www.ti.com
6.10 Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
t_RCP
Receiver Output Clock Period
t_RCP = t_TCP
t_PDC
PCLK Duty Cycle
Default Registers
SSCG[3:0] = OFF
PCLK
PCLK
23.3
45
t_CLH
LVCMOS Low-to-High Transition V_DDIO: 1.71V to 1.89V or PCLK
Time
3.0 to 3.6V,
1.3
t_CHL
LVCMOS High-to-Low Transition
Time
C_L = 8 pF (lumped load)
Default Registers
Figure 13 ⁽¹⁾
1.3
t_CLH
LVCMOS Low-to-High Transition V_DDIO: 1.71V to 1.89V or Deserializer ROUTn
Time
3.0 to 3.6V,
Data Outputs
1.6
t_CHL
LVCMOS High-to-Low Transition
Time
C_L = 8 pF (lumped load)
Default Registers
Figure 13 ⁽¹⁾
1.6
t_ROS
t_ROH
ROUT Setup Data to PCLK
ROUT Hold Data to PCLK
V_DDIO: 1.71V to 1.89V or
3.0V to 3.6V,
C_L = 8 pF (lumped load)
Default Registers
Deserializer ROUTn
Data Outputs
0.38T
0.38T
t_DD
t_DDLT
t_RJIT
Deserializer Delay
Deserializer Data Lock Time
Receiver Input Jitter Tolerance
Default Registers
Register 0x03h b[0]
(RRFB = 1)
Figure 14
Figure 12 ⁽²⁾
Figure 16, Figure 19 ⁽³⁾
(4)
10 MHz–43 MHz
10 MHz–43 MHz
43 MHz
4.571T
+8
TYP
T
50
2.0
2.0
2.4
2.4
0.5T
0.5T
MAX
100
55
2.8
2.8
3.3
3.3
4.571T 4.571T
+ 12
+ 16
10
0.53
UNIT
ns
%
ns
ns
ns
ns
ms
UI
t_RCJ
t_DPJ
t_DCCJ
fdev
fmod
Receiver Clock Jitter
Deserializer Period Jitter
Deserializer Cycle-to-Cycle Clock
Jitter
Spread Spectrum Clocking
Deviation Frequency
Spread Spectrum Clocking
Modulation Frequency
PCLK
SSCG[3:0] = OFF ^{(1) (5)}
PCLK
SSCG[3:0] = OFF ^{(1) (6)}
PCLK
SSCG[3:0] = OFF ^{(1) (7)}
LVCMOS Output Bus
SSC[3:0] = ON
Figure 17
10 MHz
43 MHz
10 MHz
43 MHz
10 MHz
43 MHz
20 MHz–43 MHz
20 MHz–43 MHz
300
550
ps
120
250
425
600
ps
320
480
320
500
ps
300
500
±0.5% to
±2.0%
%
9 kHz to
66 kHz
kHz
(1) Specification is ensured by characterization and is not tested in production.
(2) t_PLD and t_DDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
(3) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
(4) t_RJIT max (0.61UI) is limited by instrumentation and actual t_RJIT of in-band jitter at low frequency (<2 MHz) is greater 1 UI.
(5) t_DCJ is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE).
(6) t_DPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples.
(7) t_DCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
16
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