DS90UR903Q-Q1 Datasheet, PDF (10/44 Pages) Texas Instruments – 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer

DS90UR903Q-Q1, DS90UR904Q-Q1
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
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6.7 Serial Control Bus AC Timing Specifications (SCL, SDA) - I²C Compliant (See Figure 1)
Over recommended supply and temperature ranges unless otherwise specified.
PARAMETER
RECOMMENDED INPUT TIMING REQUIREMENTS⁽¹⁾
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f_SCL
t_LOW
t_HIGH
t_HD:STA
SCL Clock Frequency
SCL Low Period
SCL High Period
Hold time for a start or a repeated start
condition
f_SCL = 100 kHz
>0
100
kHz
4.7
µs
4.0
µs
4.0
µs
t_SU:STA
Set Up time for a start or a repeated
start condition
4.7
µs
t_HD:DAT Data Hold Time
t_SU:DAT Data Set Up Time
t_SU:STO Set Up Time for STOP Condition
t_r
SCL & SDA Rise Time
t_f
SCL & SDA Fall Time
C_b
Capacitive load for bus
SWITCHING CHARACTERISTICS⁽²⁾
0
3.45
µs
250
ns
4.0
µs
1000
ns
300
ns
400
pF
t_HD:DAT
t_SU:DAT
t_f
Data Hold Time
Data Set Up Time
SCL & SDA Fall Time
0
3.45
µs
250
ns
300
ns
(1) Recommended Input Timing Requirements are input specifications and not tested in production.
(2) Specification is ensured by design.
SDA
t_f
SCL
t_LOW
t_r
START
t_HD;STA
t_HD;DAT
t_f
t_HIGH
t_HD;STA
t_BUF
t_r
t_SU;DAT
t_SU;STA
REPEATED
START
t_SU;STO
STOP START
Figure 1. Serial Control Bus Timing
10
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