DS90UR903Q-Q1 Datasheet, PDF (3/44 Pages) Texas Instruments – 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer

www.ti.com
5 Pin Configuration and Functions
40 Pin Serializer – DS90UR903Q
Package RTA
Top View
DS90UR903Q-Q1, DS90UR904Q-Q1
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
V_DDIO 31
DIN[8] 32
DIN[9] 33
V_DDD 34
DIN[10] 35
DIN[11] 36
DIN[12] 37
DIN[13] 38
DIN[14] 39
DIN[15] 40
DAP = GND
DS90UR903Q
Serializer
40-Pin WQFN
(Top View)
20 NC
19 NC
18 V_DDCML
17 DOUT+
16 DOUT-
15 V_DDT
14 V_DDPLL
13 PDB
12 MODE
11 RES
DS90UR903Q Serializer Pin Functions
NAME
PIN
NUMBER
I/O, TYPE
DESCRIPTION
LVCMOS PARALLEL INTERFACE
DIN[20:0]
5, 4, 3, 2, 1, 40,
39, 38, 37, 36, 35,
33, 32, 30, 29, 28,
27, 26, 25, 24, 23
Inputs, LVCMOS
w/ pull down
Parallel data inputs.
PCLK
6
Input, LVCMOS
w/ pull down
SERIAL CONTROL BUS - I²C COMPATIBLE
Pixel Clock Input Pin. Strobe edge set by TRFB control register.
SCL
SDA
MODE
7
Input,
Open Drain
Clock line for the serial control bus communication
SCL requires an external pull-up resistor to V_DDIO.
8
Input/Output,
Open Drain
Data line for the serial control bus communication
SDA requires an external pull-up resistor to V_DDIO.
12
Input, LVCMOS
w/ pull down
I²C Mode select
MODE = H, -REQUIRED. The MODE pin must be set HIGH to allow I²C
configuration of the serializer.
ID[x]
9
Input, analog
Device ID Address Select
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 1
CONTROL AND CONFIGURATION
PDB
Power down Mode Input Pin.
13
Input, LVCMOS
w/ pull down
PDB = H, Serializer is enabled and is ON.
PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power
Down, the PLL is shutdown, and IDD is minimized. Programmed control
register data are NOT retained and reset to default values
RES
10, 11
Input, LVCMOS Reserved.
w/ pull down This pin MUST be tied LOW.
NC
22, 21, 20, 19
No Connect
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: DS90UR903Q-Q1 DS90UR904Q-Q1