DS90UR903Q-Q1 Datasheet, PDF (26/44 Pages) Texas Instruments – 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer

DS90UR903Q-Q1, DS90UR904Q-Q1
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
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8 Application and Implementation
8.1 Application Information
The DS90UR903Q/904Q chipset is intended for interface between a host (graphics processor) and a Display. It
supports a 21 bit parallel video bus for 18-bit color depth (RGB666) display format. In a RGB666 configuration,
18 color bits (R[5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) are supported
across the serial link.
The DS90UR903Q Serializer accepts a 21-bit parallel data bus. The parallel data is converted into a single
differential link. The DS90UR904Q Deserializer extracts the clock/control information from the incoming data
stream and reconstructs the 21-bit parallel data.
Camera applications are also supported by the DS90UR903Q/904Q chipset. The host controller/processsor is
connected to the deserializer, while the CMOS image sensor provides data to the serializer.
8.2 Typical Applications
Graphics
Controller
---
Video
Processor
2C
DS90UR903Q
Serializer
DS90UR904Q
Deserializer
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
PCLK
FPD-Link II
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
PCLK
Timing
Controller
SDA
SCL
Config
Confg
SDA
SCL
2C
LCD Display
Figure 26. Typical Display System Diagram
DS90UR903Q
Serializer
DS90UR904Q
Deserializer
CMOS
Image
Sensor
DIN[20:0]
PCLK
SDA
SCL
Config
Config
ROUT[20:0]
PCLK
SDA
SCL
Host
--
FPGA
--
Video
Processor
Figure 27. Typical Camera System Diagram
8.2.1 Design Requirements
For the typical design applications, use the following as input parameters.
Table 5. Design Parameters
Design Parameter
VDDIO
VDDn
AC Coupling Capacitor for DOUT± and RIN±
PCLK Frequency
Example Value
1.8 V or 3.3 V
1.8 V
100 nF
43 MHz
26
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