DS90UR903Q-Q1 Datasheet, PDF (23/44 Pages) Texas Instruments – 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer

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DS90UR903Q-Q1, DS90UR904Q-Q1
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
Register Maps (continued)
Table 3. DS90UR903Q Control Registers (continued)
ADDR
(HEX)
13
NAME
General Purpose
Control Reg
BITS
FIELD
GPCR[7]
GPCR[6]
GPCR[5]
GPCR[4]
7:0
GPCR[3]
GPCR[2]
GPCR[1]
GPCR[0]
R/W DEFAULT
RW
0x00'h
0: LOW
1: HIGH
DESCRIPTION
ADDR
(HEX)
0
1
2
NAME
I²C Device ID
Reset
RESERVED
Auto Clock
OSS Select
SSCG
Table 4. DS90UR904Q Control Registers
BITS
FIELD
7:1 DEVICE ID
0 DES ID SEL
7:3 RESERVED
2 RESERVED
1 DIGITALRESET0
0 DIGITALRESET1
7:6 RESERVED
5 AUTO_CLOCK
4 OSS_SEL
3:0 SSCG
R/W DEFAULT
DESCRIPTION
RW
0xC0'h 7-bit address of Deserializer;
0x60h
(1100_000X) default
0: Device ID is from ID[x]
1: Register I²C Device ID overrides ID[x]
0x00'h
Reserved
RW
0
Reserved
RW
0
1: Resets the device to default register values. Does not
self clear affect device I²C Bus or Device ID
RW
0
1: Digital Reset, retains all register values
self clear
00'b Reserved
RW
0
1: Output PCLK or Internal 25 MHz Oscillator clock
0: Only PCLK when valid PCLK present
Output Sleep State Select
RW
0
0: Outputs = TRI-STATE, when LOCK = L
1: Outputs = LOW , when LOCK = L
0000'b
SSCG Select
0000: Normal Operation, SSCG OFF (default)
0001: fmod (kHz) PCLK/2168, fdev ±0.50%
0010: fmod (kHz) PCLK/2168, fdev ±1.00%
0011: fmod (kHz) PCLK/2168, fdev ±1.50%
0100: fmod (kHz) PCLK/2168, fdev ±2.00%
0101: fmod (kHz) PCLK/1300, fdev ±0.50%
0110: fmod (kHz) PCLK/1300, fdev ±1.00%
0111: fmod (kHz) PCLK/1300, fdev ±1.50%
1000: fmod (kHz) PCLK/1300, fdev ±2.00%
1001: fmod (kHz) PCLK/868, fdev ±0.50%
1010: fmod (kHz) PCLK/868, fdev ±1.00%
1011: fmod (kHz) PCLK/868, fdev ±1.50%
1100: fmod (kHz) PCLK/868, fdev ±2.00%
1101: fmod (kHz) PCLK/650, fdev ±0.50%
1110: fmod (kHz) PCLK/650, fdev ±1.00%
1111: fmod (kHz) PCLK/650, fdev ±1.50%
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