DS90UR903Q-Q1 Datasheet, PDF (27/44 Pages) Texas Instruments – 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer

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DS90UR903Q-Q1, DS90UR904Q-Q1
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
8.2.2 Detailed Design Procedure
8.2.2.1 Typical Application Connection
Figure 28 shows a typical connection of the DS90UR903Q Serializer for an 18-bit application. The CML outputs
require 0.1 μF AC coupling capacitors to the line. The line driver includes internal termination. Bypass capacitors
are placed near the power supply Terminals. System GPO (General Purpose Output) signals control the PDB
and MODE Terminals. The interface to the host is with 1.8 V LVCMOS levels, thus the VDDIO Terminal is
connected also to the 1.8V rail. The optional Serial Bus control is used in this example, thus SCL and SDA are
connected to the system and the ID[x] Terminal is connected to a resistor divider.
VDDIO
C12 C8
FB1
C3
LVCMOS
Parallel
Bus
LVCMOS
Control
Interface
DS90UR903Q (SER)
VDDIO
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
DIN10
DIN11
DIN12
DIN13
DIN14
DIN15
DIN16
DIN17
DIN18
DIN19
DIN20
PCLK
MODE
PDB
VDDT
C4
FB2
VDDPLL
C10 C5
FB3
VDDCML
C11 C6
FB4
VDDD
C7
FB5
DOUT+
DOUT-
ID[X]
C1
C2
1.8V
10 k:
RID
1.8V
C9 C13
Serial
FPD-Link II
Interface
I2C
Bus
Interface
FB6
FB7
Optional
VDDIO
RPU
C14
RPU
SCL
SDA
C15
Optional
RES
DAP (GND)
NOTE:
C1 - C2 = 0.1 PF (50 WV)
C3 - C9 = 0.1 PF
C10 - C13 = 4.7 PF
C14 - C15 = >100 pF
RPU = 1 k: to 4.7 k:
RID (see ID[x] Resistor Value Table)
FB1 - FB7: Impedance = 1 k: (@ 100 MHz)
low DC resistance (<1:)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
Figure 28. DS90UR903Q Typical Connection Diagram — Pin Control
40-Pin WQFN (RTA Package)
Figure 29 shows a typical connection of the DS90UR904Q Deserializer for an 18-bit application. The CML inputs
utilize 0.1 μF coupling capacitors to the line and the receiver provides internal termination. Bypass capacitors are
placed near the power supply Terminals. System GPO (General Purpose Output) signals control the PDB and
the MODE Terminals. The interface to the target display is with 3.3V LVCMOS levels, thus the VDDIO Terminal
is connected to the 3.3 V rail. The optional Serial Bus control is used in this example, thus SCL and SDA are
connected to the system and the ID[x] Terminal is connected to a resistor divider. LOCK is monitored by a
system GPI (General Purpose Input).
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