DS90UR903Q-Q1 Datasheet, PDF (29/44 Pages) Texas Instruments – 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer

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DS90UR903Q-Q1, DS90UR904Q-Q1
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
8.2.2.2 AC Coupling
The SER/DES supports only AC-coupled interconnects through an integrated DC balanced decoding scheme.
External AC coupling capacitors must be placed in series in the FPD-Link II signal path as illustrated in
Figure 30.
D_OUT+
D
D_OUT-
R_IN+
R
R_IN-
Figure 30. AC-Coupled Connection
For high-speed FPD-Link II transmissions, the smallest available package should be used for the AC coupling
capacitor. This will help minimize degradation of signal quality due to package parasitics. The I/O’s require a 100
nF AC coupling capacitors to the line.
8.2.2.3 Power Up Requirements and PDB PIN
When power is applied, the VDDIO supply needs to reach the expected operating voltage (1.8V or 3.3V) before
the other supplies (VDDn) begin to ramp. It is also required to delay and release the PDB input signal after VDD
(VDDn and VDDIO) power supplies have settled to the recommended operating voltages. A external RC network
can be connected to the PDB pin to ensure PDB arrives after all the VDD have stabilized.
VDDIO
1.8V OR 3.3V
VDD_CORE,
All other 1.8V Supplies
PDB
1.8V
1.8V OR 3.3V
Figure 31. Power Up Sequence
8.2.2.4 Transmission Media
The Ser/Des chipset is intended to be used over a wide variety of balanced cables depending on distance and
signal quality requirements. The Ser/Des employ internal termination providing a clean signaling environment.
The interconnect for FPD-Link II interface should present a differential impedance of 100 Ohms. Use of cables
and connectors that have matched differential impedance will minimize impedance discontinuities. Shielded or
un-shielded cables may be used depending upon the noise environment and application requirements. The
chipset's optimum cable drive performance is achieved at 43 MHz at 10 meters length. The maximum signaling
rate increases as the cable length decreases. Therefore, the chipset supports 50 MHz at shorter distances. Other
cable parameters that may limit the cable's performance boundaries are: cable attenuation, near-end crosstalk
and pair-to-pair skew.
For obtaining optimal performance, we recommend:
• Use Shielded Twisted Pair (STP) cable
• 100Ω differential impedance and 24 AWG (or lower AWG) cable
• Low skew, impedance matched
• Ground and/or terminate unused conductors
Figure 32 shows the Typical Performance Characteristics demonstrating various lengths and data rates using
Rosenberger HSD and Leoni DACAR 538 Cable.
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