DS90UR903Q-Q1 Datasheet, PDF (15/44 Pages) Texas Instruments – 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer

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DS90UR903Q-Q1, DS90UR904Q-Q1
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
6.9 Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
t_LHT
CML Low-to-High Transition
R_L = 100Ω
Time
Figure 3
t_HLT
CML High-to-Low Transition
R_L = 100Ω
Time
Figure 3
t_DIS
Data Input Setup to PCLK
Serializer Data Inputs
t_DIH
Data Input Hold from PCLK
Figure 9
t_PLD
Serializer PLL Lock Time
R_L = 100Ω^{(1) (2)}
t_SD
Serializer Delay
R_T = 100Ω
PCLK = 10–43 MHz
Register 0x03h b[0] (TRFB = 1)
Figure 11
2.0
2.0
6.386T
+5
t_JIND
Serializer Output Deterministic Serializer output intrinsic deterministic
Jitter
jitter . Measured (cycle-cycle) with
PRBS-7 test pattern
PCLK = 43 MHz^{(3) (4)}
t_JINR
Serializer Output Random Jitter Serializer output intrinsic random jitter
(cycle-cycle). Alternating-1,0 pattern.
PCLK = 43 MHz^{(3) (4)}
t_JINT
Peak-to-peak Serializer Output Serializer output peak-to-peak jitter
Jitter
includes deterministic jitter, random
jitter, and jitter transfer from serializer
input. Measured (cycle-cycle) with
PRBS-7 test pattern.
PCLK = 43 MHz^{(3) (4)}
λ_STXBW
Serializer Jitter Transfer Function PCLK = 43 MHz
-3 dB Bandwidth
Default Registers
Figure 18 ⁽³⁾
δ_STX
Serializer Jitter Transfer Function PCLK = 43 MHz
(Peaking)
Default Registers
Figure 18 ⁽³⁾
δ_STXf
Serializer Jitter Transfer Function PCLK = 43 MHz
(Peaking Frequency)
Default Registers
Figure 18 ⁽³⁾
TYP
150
150
1
6.386T
+ 12
0.13
0.04
0.396
1.90
0.944
500
MAX
330
330
2
6.386T
+ 19.7
UNIT
ps
ps
ns
ns
ms
ns
UI
UI
UI
MHz
dB
kHz
(1) t_PLD and t_DDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
(2) Specification is ensured by design.
(3) Typical values represent most likely parametric norms at 1.8V or 3.3V, T_A = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
(4) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
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