DS80PCI402_15 Datasheet, PDF (5/54 Pages) Texas Instruments – 2.5-Gbps / 5.0-Gbps / 8.0-Gbps 4-Lane PCI-Express Repeater With Equalization and De-Emphasis

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DS80PCI402
SNLS324E – APRIL 2011 – REVISED JANUARY 2015
Pin Functions^(1)(2)(3)(4) (continued)
PIN
NAME
I/O, TYPE
NUMBER
DESCRIPTION
ALL_DONE
O, 2- Valid register load status output
27
LEVEL, HIGH = External EEPROM load failed or incomplete
LVCMOS LOW = External EEPROM load passed
ENSMB = 0 (PIN MODE)
EQA0, EQA1,
EQB0, EQB1
20, 19, 46,
47
I, 4-LEVEL,
LVCMOS
EQA[1:0] and EQB[1:0] control the level of equalization on the input pins. The pins are
active only when ENSMB is deasserted (low). The 8 channels are organized into two
banks. Bank A is controlled with the EQA[1:0] pins and bank B is controlled with the
EQB[1:0] pins. When ENSMB goes high the SMBus registers provide independent
control of each channel. The EQB[1:0] pins are converted to SMBUS AD2/AD3 inputs.
See Table 2.
DEMA0, DEMA1,
DEMB0, DEMB1
49, 50, 53,
54
I, 4-LEVEL,
LVCMOS
DEMA[1:0] and DEMB[1:0] control the level of de-emphasis of the output driver. The
pins are only active when ENSMB is deasserted (low). The 8 channels are organized
into two banks. Bank A is controlled with the DEMA[1:0] pins and bank B is controlled
with the DEMB[1:0] pins. When ENSMB goes high the SMBus registers provide
independent control of each channel. The DEMA[1:0] pins are converted to SMBUS
SCL/SDA and DEMB[1:0] pins are converted to AD0, AD1 inputs.
See Table 3.
CONTROL PINS — BOTH PIN AND SMBUS MODES (LVCMOS)
RATE
RATE control pin selects GEN 1,2 and GEN 3 operating modes.
21
I, 4-LEVEL,
LVCMOS
Tie 1 kΩ to GND = GEN 1,2
FLOAT = AUTO Rate Select of Gen1/2 and Gen3 with de-emphasis
Tie 20 kΩ to GND = GEN 3 without de-emphasis
Tied 1 kΩ to VDD = RESERVED
RXDET
22
I, 4-LEVEL,
LVCMOS
The RXDET pin controls the receiver detect function. Depending on the input level, a 50-
Ω or > 50-kΩ termination to the power rail is enabled.
See Table 4.
LPBK
Controls the loopback function
23
I, 4-LEVEL, Tie 1 kΩ to GND = Root Complex Loopback (INA_n to OUTB_n)
LVCMOS Float = Normal Operation
Tie 1 kΩ to VDD = End-point Loopback (INB_n to OUTA_n)
VDD_SEL
Controls the internal regulator
25
I, LVCMOS
FLOAT = 2.5-V mode
Tie GND = 3.3-V mode
See Figure 14.
SD_TH
26
I, 4-LEVEL, Controls the internal Signal Detect Threshold.
LVCMOS See Table 5.
PRSNT
52
I, 2-LEVEL,
LVCMOS
Cable Present Detect input. High when a cable is not present per PCIe Cabling Spec.
1.0. Puts part into low power mode. When LOW (normal operation) part is enabled.
See Table 4.
POWER
VIN
24
Power
In 3.3-V mode, feed 3.3 V to VIN
In 2.5-V mode, leave floating
VDD
9, 14, 36,
41, 51
Power
Power supply pins
2.5-V mode, connect to 2.5-V supply
3.3-V mode, connect 0.1-µF capacitor to each VDD pin (output of LDO)
GND
DAP
Power Ground pad (DAP - die attach pad)
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