DS80PCI402_15 Datasheet, PDF (45/54 Pages) Texas Instruments – 2.5-Gbps / 5.0-Gbps / 8.0-Gbps 4-Lane PCI-Express Repeater With Equalization and De-Emphasis

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11 Layout
DS80PCI402
SNLS324E – APRIL 2011 – REVISED JANUARY 2015
11.1 Layout Guidelines
11.1.1 PCB Layout Considerations for Differential Pairs
The differential inputs and outputs are designed with 100-Ω differential terminations. Therefore, they should be
connected to interconnects with controlled differential impedance of approximately 85-110 Ω. It is preferable to
route differential lines primarily on one layer of the board, particularly for the input traces. The use of vias should
be avoided if possible. If vias must be used, they should be used sparingly and must be placed symmetrically for
each side of a given differential pair. Whenever differential vias are used, the layout must also provide for a low
inductance path for the return currents as well. Route the differential signals away from other signals and noise
sources on the printed circuit board. To minimize the effects of crosstalk, a 5:1 ratio or greater should be
maintained between inter-pair spacing and trace width. See AN-1187 Leadless Leadframe Package (LLP)
Application Report (SNOA401) for additional information on QFN (WQFN) packages.
The DS80PCI402 pinout promotes easy high speed routing and layout. To optimize DS80PCI402 performance
refer to the following guidelines:
1. Place local VIN and VDD capacitors as close as possible to the device supply pins. Often the best location is
directly under the DS80PCI402 pins to reduce the inductance path to the capacitor. In addition, bypass
capacitors may share a via with the DAP GND to minimize ground loop inductance.
2. Differential pairs going into or out of the DS80PCI402 should have adequate pair-to-pair spacing to minimize
crosstalk.
3. Use return current via connections to link reference planes locally. This ensures a low inductance return
current path when the differential signal changes layers.
4. Optimize the via structure to minimize trace impedance mismatch.
5. Place GND vias around the DAP perimeter to ensure optimal electrical and thermal performance.
6. Use small body size AC coupling capacitors when possible — 0402 or smaller size is preferred. The AC
coupling capacitors should be placed closer to the Rx on the channel.
Figure 15 depicts different transmission line topologies which can be used in various combinations to achieve the
optimal system performance. Impedance discontinuities at the differential via can be minimized or eliminated by
increasing the swell around each hole and providing for a low inductance return current path. When the via
structure is associated with thick backplane PCB, further optimization such as back drilling is often used to
reduce the detrimental high-frequency effects of stubs on the signal path.
11.2 Layout Example
EXTERNAL MICROSTRIP
20 mils
INTERNAL STRIPLINE
100 mils
20 mils
VDD
VDD
VDD
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
19
54
20
53
21
52
22
51
23
BOTTOM OF PKG
50
GND
24
49
25
48
26
47
27
46
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
VDD
VDD
Figure 15. Typical Routing Options
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